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MROD_X_Out

Gen1us

Documentation for architecture MROD_X_Out/Gen1us/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Gen1us'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     TicksPer_Us :  positive := 40);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     O     : out    std_logic;
   14  --     Rst_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Gen1us is
   19  
   20  begin
   21     Process (Clk, Rst_n)
   22        Variable Count: Unsigned(7 downto 0);
   23     Begin       
   24        If Rst_n = '0' Then
   25           Count := (Others => '0');
   26           O <= '0';
   27        ElsIf Rising_Edge(Clk) Then
   28           Count := Count + 1;
   29           If Count = To_Unsigned(TicksPer_us,8) then
   30              Count := (Others => '0');
   31              O <= '1';
   32           Else
   33              O <= '0';
   34           End If;
   35        End If;
   36     End Process;
   37  end architecture a0 ; -- of Gen1us
   38  
   39