Generated by EASE/HDL for peterj on Mon Jul 02 10:55:25 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Busy_mask'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Busy : out std_logic; 11 -- Busy_1A : in std_logic; 12 -- Busy_1B : in std_logic; 13 -- Busy_2A : in std_logic; 14 -- Busy_2B : in std_logic; 15 -- Busy_3A : in std_logic; 16 -- Busy_3B : in std_logic; 17 -- Busy_4A : in std_logic; 18 -- Busy_4B : in std_logic; 19 -- Inc_RunN : in std_logic; 20 -- Mask : in std_logic_vector(9 downto 0); 21 -- TTC_BusyReq : in std_logic); 22 -- 23 -- EASE/HDL end ---------------------------------------------------------------- 24 25 architecture a0 of Busy_mask is 26 27 begin 28 29 Busy <= (Busy_1A And Mask(0)) Or 30 (Busy_1B And Mask(1)) Or 31 (Busy_2A And Mask(2)) Or 32 (Busy_2B And Mask(3)) Or 33 (Busy_3A And Mask(4)) Or 34 (Busy_3B And Mask(5)) Or 35 (Busy_4A And Mask(6)) Or 36 (Busy_4B And Mask(7)) Or 37 (TTC_BusyReq And Mask(8)) Or 38 Mask(9) Or 39 Inc_RunN; 40 41 end architecture a0 ; -- of Busy_mask 42 43