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MROD_X_Out

Extended_EV_ID_Cnt

Documentation for architecture MROD_X_Out/Extended_EV_ID_Cnt/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Extended_EV_ID_Cnt'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n    :  Positive := 8;
   11  --     init :  string := "00");
   12  --   port(
   13  --     Clk   : in     std_logic;
   14  --     D     : in     std_logic_vector(n-1 downto 0);
   15  --     Inc   : in     std_logic;
   16  --     Ld    : in     std_logic;
   17  --     Q     : out    std_logic_vector(n-1 downto 0);
   18  --     Rst_n : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of Extended_EV_ID_Cnt is
   23  
   24  begin
   25     Process (Clk, Rst_n)
   26        Variable Cnt: Unsigned (n-1 Downto 0);
   27     Begin
   28        If Rst_n = '0' Then
   29           Cnt := Unsigned(HexToStdLogicVector(Init,n));
   30        ElsIf Rising_Edge(Clk) Then
   31           If Ld = '1' Then
   32              Cnt := Unsigned(D);
   33           ElsIf Inc = '1' Then
   34              Cnt := Cnt + 1;
   35           End If;
   36        End If;
   37        Q <= Std_logic_Vector(Cnt);
   38     End Process;
   39  end architecture a0 ; -- of Extended_EV_ID_Cnt
   40  
   41