Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007
Back Index MROD_X_Out DS2401_Statem

Documentation for architecture MROD_X_Out/DS2401_Statem/a0

Contents Side Data Generated HDL

Fsm Conditions:

Label Name Usage VHDL
1 
Rst_n = '0'
1 
Rd = '1'
1 
CntUs = Trstl
1 
CntUs = (Tpdh + Tpdl)
1 
CntUs = Tlow_wr
1 
CntUs = Trec And
CntBits < (NumOfCmdBits - 1)
1 
CntUs = Tds2401samplingwnd
1 
CntUs = Trec And
CntBits = (NumOfCmdBits - 1)
1 
CntUs = Tlow_rd
1 
CntUs = Tpresample
1 
CntUs = Tpostsample And
CntBits < (NumOfDataBits -1)
1 
CntUs = Tpostsample And
CntBits = (NumOfDataBits -1)

Fsm Actions:

Label Name Usage VHDL
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
CntUs := 0;
1 
CntBits := 0;
1 
DS2401 <= '0';
1 
Sample <= '0';
1 
CntBits := 0;
CntUsInc9 
If Tick1Us = '1' Then
   CntUs := CntUs + 1;
End If;
1 
CntUs := 0;
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
CntBits := 0;
1 
CntUs := 0;
1 
DS2401 <= '0';
1 
Sample <= '0';
1 
CntUs := 0;
1 
DS2401 <= DS_Command(CntBits);
1 
Sample <= '0';
1 
CntUs := 0;
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
CntUs := 0;
1 
DS2401 <= '0';
1 
Sample <= '0';
1 
CntBits := 0;
1 
CntUs := 0;
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
CntUs := 0;
1 
DS2401 <= '1';
1 
Sample <= '1';
1 
CntUs := 0;
1 
DS2401 <= '1';
1 
Sample <= '0';
1 
CntUs := 0;
1 
CntUs := 0;
1 
CntUs := 0;
CntBitsInc2 
CntBits := CntBits + 1;
1 
CntUs := 0;
1 
CntUs := 0;
1 
CntBits := 0;