Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007
Back Index MROD_X_Out Date_Revision_ID_Reg

Documentation for architecture MROD_X_Out/Date_Revision_ID_Reg/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Date_Revision_ID_Reg'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Date_ID     :  integer := 0;
   11  --     Revision_ID :  integer := 0);
   12  --   port(
   13  --     Reg5d : out    std_logic_vector(31 downto 0));
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of Date_Revision_ID_Reg is
   18  
   19  begin
   20     Reg5d(31 downto 8) <= Std_Logic_Vector(To_Unsigned(Date_ID,24));
   21     Reg5d(7 downto 0) <= Std_Logic_Vector(To_Unsigned(Revision_ID,8));
   22  end architecture a0 ; -- of Date_Revision_ID_Reg
   23  
   24