Back

Index

MROD_X_Out

Fifo511w8

Documentation for architecture MROD_X_Out/Fifo511w8/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Fifo511w8'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D        : in     std_logic_vector(7 downto 0);
   11  --     Empty    : out    std_logic;
   12  --     Full     : out    std_logic;
   13  --     HalfFull : out    std_logic;
   14  --     Q        : out    std_logic_vector(7 downto 0);
   15  --     RdClk    : in     std_logic;
   16  --     RdReq    : in     std_logic;
   17  --     Rst      : in     std_logic;
   18  --     WrClk    : in     std_logic;
   19  --     WrReq    : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of Fifo511w8 is
   24  
   25     component fifo_511x8
   26        port (
   27           din: IN std_logic_VECTOR(7 downto 0);
   28           rd_clk: IN std_logic;
   29           rd_en: IN std_logic;
   30           rst: IN std_logic;
   31           wr_clk: IN std_logic;
   32           wr_en: IN std_logic;
   33           dout: OUT std_logic_VECTOR(7 downto 0);
   34           empty: OUT std_logic;
   35           full: OUT std_logic;
   36           prog_full: OUT std_logic);
   37     end component;
   38  
   39  begin
   40  
   41    uc1: fifo_511x8
   42       port map (
   43           din => D,
   44           rd_clk => RdClk,
   45           rd_en => RdReq,
   46           rst => Rst,
   47           wr_clk => WrClk,
   48           wr_en => WrReq,
   49           dout => Q,
   50           empty => Empty,
   51           full => Full,
   52           prog_full => HalfFull
   53       );
   54  
   55  end architecture a0 ; -- of Fifo511w8
   56  
   57