Back

Index

MROD_X_Out

RegEn_Impl

Documentation for architecture MROD_X_Out/RegEn_Impl/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegEn_Impl'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n         :  positive := 8;
   11  --     Init      :  string := "00000000";
   12  --     Implement :  string := "FF");
   13  --   port(
   14  --     Clk   : in     std_logic;
   15  --     D     : in     std_logic_vector(n-1 downto 0);
   16  --     En_n  : in     std_logic;
   17  --     Q     : out    std_logic_vector(n-1 downto 0);
   18  --     Rst_n : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of RegEn_Impl is
   23  
   24  begin
   25  
   26     Process (Clk, Rst_n)
   27     Begin
   28        If Rst_n = '0' Then
   29           Q <= HexToStdLogicVector(Init,n);
   30        ElsIf Rising_Edge(Clk) Then
   31           If En_n = '0' Then
   32              Q <= D And HexToStdLogicVector(Implement,n);
   33           End If;
   34        End If;    
   35     End Process;
   36  
   37  end architecture a0 ; -- of RegEn_Impl
   38  
   39