Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007

Documentation for architecture MROD_X_Out/OpenDrain/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'OpenDrain'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     I : in     std_logic;
   11  --     O : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of OpenDrain is
   16  
   17  begin
   18     Process (I)
   19     Begin
   20        If I = '0' Then
   21           O <= '0';
   22        Else
   23           O <= 'Z';
   24        End If;      
   25     End Process;
   26  end architecture a0 ; -- of OpenDrain
   27  
   28