Back

Index

MROD_X_Out

RstAndFull

Documentation for architecture MROD_X_Out/RstAndFull/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RstAndFull.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RstAndFull' :
    5  -- 
    6  --   port(
    7  --     FifoFull  : in     std_logic;
    8  --     OutpFull  : out    std_logic;
    9  --     OutpRst_n : out    std_logic;
   10  --     Rst_n     : in     std_logic;
   11  --     URESET_n  : in     std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of RstAndFull is
   16  
   17  begin
   18     -- S-Link Fifo and Pipeline Reset also when there is a URESET_n
   19     OutpRst_n <= '0' when (Rst_n = '0' or URESET_n = '0') else '1';
   20  
   21     -- When no S-Link LSC is installed and when a LRst is / was
   22     -- asserted then URESET_n becomes asserted and stays
   23     -- asserted since LDOWN_n will never be de-assereted (there
   24     -- is no LSC). This causes the S-Link_FIFO to stay in reset
   25     -- (thus signalling never full). However, data comming from the 
   26     -- eventbuilder should be signalled that the output is full.
   27     OutpFull <= '1' when (Rst_n = '0' or URESET_n = '0' or FifoFull = '1') else '0';
   28  
   29  end architecture a0 ; -- of RstAndFull
   30  
   31