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MROD_X_Out

FlushMode

Documentation for architecture MROD_X_Out/FlushMode/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FlushMode'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Flush           : in     std_logic;
   11  --     Full_I          : in     std_logic;
   12  --     Full_O          : out    std_logic;
   13  --     HalfFull        : in     std_logic;
   14  --     S_LINK_HalfFull : out    std_logic;
   15  --     URESET_n        : in     std_logic;
   16  --     WrReq_I         : in     std_logic;
   17  --     WrReq_O         : out    std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of FlushMode is
   22  
   23     signal HalfFullInternal: std_logic;
   24  begin
   25  
   26     --When no S-Link LSC is installed and when a LRst is / was
   27     --asserted then URESET_n becomes asserted and stays
   28     --asserted since LDOWN_n will never be de-assereted (there
   29     --is no LSC). This causes the S-Link_FIFO to stay in reset
   30     --(thus signalling never full). However, data comming from the 
   31     --eventbuilder should be signalled that the output is full.
   32     --Therefore signal HalfFull when the FIFO is being reset.
   33     --Note: Full is not signalled during reset since this will stall
   34     --the Sharc access (no acknowledge).
   35     
   36     HalfFullInternal <= '1' when (HalfFull = '1' Or URESET_n = '0') else '0';
   37     
   38     Process (Flush, Full_I, WrReq_I, HalfFullInternal)
   39     Begin
   40        If Flush = '1' Then
   41           Full_O <= '0';
   42           S_LINK_HalfFull <= '0';
   43           WrReq_O <= '0';
   44        Else
   45           Full_O <= Full_I;
   46           S_LINK_HalfFull <= HalfFullInternal;
   47           WrReq_O <= WrReq_I;
   48        End If;
   49     End Process;
   50  end architecture a0 ; -- of FlushMode
   51  
   52