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MROD_X_Out

RegPst

Documentation for architecture MROD_X_Out/RegPst/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'RegPst.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'RegPst' :
    5  -- 
    6  --   generic(
    7  --     n :  positive := 8 );
    8  --   port(
    9  --     Clk   : in     std_logic;
   10  --     D     : in     std_logic_vector(n-1 downto 0);
   11  --     Pst_n : in     std_logic;
   12  --     Q     : out    std_logic_vector(n-1 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of RegPst is
   17  
   18  BEGIN
   19     Process (Clk, Pst_n)
   20     Begin
   21        If Pst_n = '0' Then
   22           Q <= (others => '1');
   23        ElsIf Rising_Edge(Clk) Then
   24           Q <= D;
   25        End If;    
   26     End Process;
   27  end architecture a0 ; -- of RegPst
   28