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MROD_X_Out

Reg1PstEn

Documentation for architecture MROD_X_Out/Reg1PstEn/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Reg1PstEn'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     D     : in     std_logic;
   12  --     En_n  : in     std_logic;
   13  --     Pst_n : in     std_logic;
   14  --     Q     : out    std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Reg1PstEn is
   19  
   20  BEGIN
   21     Process (Clk, Pst_n)
   22     Begin
   23        If Pst_n = '0' Then
   24           Q <= '1';
   25        -- Need function Rising_Edge because we don't want the event
   26        -- 'H' -> '1' to clock the flip-flop
   27        ElsIf Rising_Edge(Clk) Then
   28           If En_n = '0' Then
   29              Q <= D;
   30           End If;
   31        End If;
   32     End Process;
   33  end architecture a0 ; -- of Reg1PstEn
   34