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MROD_X_Out

PagedFifo_RAM_256x25

Documentation for architecture MROD_X_Out/PagedFifo_RAM_256x25/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'PagedFifo_RAM_256x25.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'PagedFifo_RAM_256x25' :
    5  -- 
    6  --   port(
    7  --     Address : in     std_logic_vector(7 downto 0);
    8  --     Data    : in     std_logic_vector(24 downto 0);
    9  --     Inclock : in     std_logic;
   10  --     Q       : out    std_logic_vector(24 downto 0);
   11  --     WE      : in     std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of PagedFifo_RAM_256x25 is
   16     component ramdq_256x25
   17        port (
   18        addr: IN std_logic_VECTOR(7 downto 0);
   19        clk: IN std_logic;
   20        din: IN std_logic_VECTOR(24 downto 0);
   21        dout: OUT std_logic_VECTOR(24 downto 0);
   22        we: IN std_logic);
   23     end component;
   24  begin
   25  
   26     Inst_1: ramdq_256x25
   27        Port Map (
   28           addr => Address,
   29           we => WE,
   30           clk => Inclock,
   31           din => Data,
   32           dout => Q
   33        );
   34  end architecture a0 ; -- of PagedFifo_RAM_256x25
   35