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MROD_X_Out

Dec_TstA32

Documentation for architecture MROD_X_Out/Dec_TstA32/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'Dec_TstA32.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'Dec_TstA32' :
    5  -- 
    6  --   port(
    7  --     A32         : in     std_logic;
    8  --     Adr         : in     std_logic_vector(31 downto 0);
    9  --     BLT         : in     std_logic;
   10  --     Clk         : in     std_logic;
   11  --     Cs_TstA32_n : out    std_logic;
   12  --     DATA        : in     std_logic;
   13  --     DECODE      : in     std_logic;
   14  --     NPRIV       : in     std_logic;
   15  --     PROG        : in     std_logic;
   16  --     Rst_n       : in     std_logic;
   17  --     SUPER       : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of Dec_TstA32 is
   22  
   23  begin
   24     Process (Clk, Rst_n)
   25     Begin
   26        If Rst_n = '0' Then
   27           Cs_TstA32_n <= '1';
   28        ElsIf Rising_Edge(Clk) Then
   29           --the Chip Select signal is continuously updated but as soon as the
   30           --DECODE signal arrives the result is holded for the duration of DECODE
   31           If DECODE = '0' Then
   32              --For test porposes decode if address = 0xEEXXXXXX
   33              If A32 = '1' And
   34                 (((SUPER = '1' Or NPRIV = '1') And (PROG = '1' Or DATA = '1')) Or BLT = '1') And
   35                 Adr(31 Downto 24) = "11101110" Then
   36                 Cs_TstA32_n <= '0';
   37              Else
   38                 Cs_TstA32_n <= '1';
   39              End If;
   40           End If;
   41        End If;
   42     End Process;
   43  end architecture a0 ; -- of Dec_TstA32
   44