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MROD_X_Out

AddressDecoder

Documentation for architecture MROD_X_Out/AddressDecoder/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'AddressDecoder.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'AddressDecoder' :
    5  -- 
    6  --   port(
    7  --     Adr     : in     std_logic_vector(22 downto 0);
    8  --     MS0_n   : in     std_logic;
    9  --     Sel0_n  : out    std_logic;
   10  --     Sel10_n : out    std_logic;
   11  --     Sel11_n : out    std_logic;
   12  --     Sel12_n : out    std_logic;
   13  --     Sel13_n : out    std_logic;
   14  --     Sel14_n : out    std_logic;
   15  --     Sel15_n : out    std_logic;
   16  --     Sel16_n : out    std_logic;
   17  --     Sel17_n : out    std_logic;
   18  --     Sel18_n : out    std_logic;
   19  --     Sel19_n : out    std_logic;
   20  --     Sel1A_n : out    std_logic;
   21  --     Sel1B_n : out    std_logic;
   22  --     Sel1C_n : out    std_logic;
   23  --     Sel1D_n : out    std_logic;
   24  --     Sel1E_n : out    std_logic;
   25  --     Sel1F_n : out    std_logic;
   26  --     Sel1_n  : out    std_logic;
   27  --     Sel20_n : out    std_logic;
   28  --     Sel21_n : out    std_logic;
   29  --     Sel22_n : out    std_logic;
   30  --     Sel23_n : out    std_logic;
   31  --     Sel24_n : out    std_logic;
   32  --     Sel25_n : out    std_logic;
   33  --     Sel26_n : out    std_logic;
   34  --     Sel27_n : out    std_logic;
   35  --     Sel28_n : out    std_logic;
   36  --     Sel29_n : out    std_logic;
   37  --     Sel2A_n : out    std_logic;
   38  --     Sel2B_n : out    std_logic;
   39  --     Sel2C_n : out    std_logic;
   40  --     Sel2D_n : out    std_logic;
   41  --     Sel2_n  : out    std_logic;
   42  --     Sel3F_n : out    std_logic;
   43  --     Sel3_n  : out    std_logic;
   44  --     Sel4_n  : out    std_logic;
   45  --     Sel5_n  : out    std_logic;
   46  --     Sel6_n  : out    std_logic;
   47  --     Sel7_n  : out    std_logic;
   48  --     Sel8_n  : out    std_logic;
   49  --     Sel9_n  : out    std_logic;
   50  --     SelA_n  : out    std_logic;
   51  --     SelB_n  : out    std_logic;
   52  --     SelC_n  : out    std_logic;
   53  --     SelD_n  : out    std_logic;
   54  --     SelE_n  : out    std_logic;
   55  --     SelF_n  : out    std_logic);
   56  -- 
   57  -- EASE/HDL end ----------------------------------------------------------------
   58  
   59  architecture a0 of AddressDecoder is
   60  
   61  begin
   62  
   63     Process (Adr, MS0_n)
   64        Variable Address: Integer;
   65     Begin
   66        Address := To_Integer(Unsigned(Adr(22 DOWNTO 1)));
   67        Sel0_n <= '1';
   68        Sel1_n <= '1';
   69        Sel2_n <= '1';
   70        Sel3_n <= '1';
   71        Sel4_n <= '1';
   72        Sel5_n <= '1';
   73        Sel6_n <= '1';
   74        Sel7_n <= '1';
   75        Sel8_n <= '1';
   76        Sel9_n <= '1';
   77        SelA_n <= '1';
   78        SelB_n <= '1';
   79        SelC_n <= '1';
   80        SelD_n <= '1';
   81        SelE_n <= '1';
   82        SelF_n <= '1';
   83        Sel10_n <= '1';
   84        Sel11_n <= '1';
   85        Sel12_n <= '1';
   86        Sel13_n <= '1';
   87        Sel14_n <= '1';
   88        Sel15_n <= '1';
   89        Sel16_n <= '1';
   90        Sel17_n <= '1';
   91        Sel18_n <= '1';
   92        Sel19_n <= '1';
   93        Sel1A_n <= '1';
   94        Sel1B_n <= '1';
   95        Sel1C_n <= '1';
   96        Sel1D_n <= '1';
   97        Sel1E_n <= '1';
   98        Sel1F_n <= '1';
   99        Sel20_n <= '1';
  100        Sel21_n <= '1';
  101        Sel22_n <= '1';
  102        Sel23_n <= '1';
  103        Sel24_n <= '1';
  104        Sel25_n <= '1';
  105        Sel26_n <= '1';
  106        Sel27_n <= '1';
  107        Sel28_n <= '1';
  108        Sel29_n <= '1';
  109        Sel2A_n <= '1';
  110        Sel2B_n <= '1';
  111        Sel2C_n <= '1';
  112        Sel2D_n <= '1';
  113  
  114        Sel3F_n <= '1'; -- Reg3F is register reading spare inputs
  115  
  116        If MS0_n = '0' Then
  117           If Address = 16#0# Then
  118              Sel0_n <= '0';
  119           ElsIf Address = 16#1# Then
  120              Sel1_n <= '0';
  121           ElsIf Address = 16#2# Then
  122              Sel2_n <= '0';
  123           ElsIf Address = 16#3# Then
  124              Sel3_n <= '0';
  125           ElsIf Address = 16#4# Then
  126              Sel4_n <= '0';
  127           ElsIf Address = 16#5# Then
  128              Sel5_n <= '0';
  129           ElsIf Address = 16#6# Then
  130              Sel6_n <= '0';
  131           ElsIf Address = 16#7# Then
  132              Sel7_n <= '0';
  133           ElsIf Address = 16#8# Then
  134              Sel8_n <= '0';
  135           ElsIf Address = 16#9# Then
  136              Sel9_n <= '0';
  137           ElsIf Address = 16#0A# Then
  138              SelA_n <= '0';
  139           ElsIf Address = 16#0B# Then
  140              SelB_n <= '0';
  141           ElsIf Address = 16#0C# Then
  142              SelC_n <= '0';
  143           ElsIf Address = 16#0D# Then
  144              SelD_n <= '0';
  145           ElsIf Address = 16#0E# Then
  146              SelE_n <= '0';
  147           ElsIf Address = 16#0F# Then
  148              SelF_n <= '0';
  149           ElsIf Address = 16#10# Then
  150              Sel10_n <= '0';
  151           ElsIf Address = 16#11# Then
  152              Sel11_n <= '0';
  153           ElsIf Address = 16#12# Then
  154              Sel12_n <= '0';
  155           ElsIf Address = 16#13# Then
  156              Sel13_n <= '0';
  157           ElsIf Address = 16#14# Then
  158              Sel14_n <= '0';
  159           ElsIf Address = 16#15# Then
  160              Sel15_n <= '0';
  161           ElsIf Address = 16#16# Then
  162              Sel16_n <= '0';
  163           ElsIf Address = 16#17# Then
  164              Sel17_n <= '0';
  165           ElsIf Address = 16#18# Then
  166              Sel18_n <= '0';
  167           ElsIf Address = 16#19# Then
  168              Sel19_n <= '0';
  169           ElsIf Address = 16#1A# Then
  170              Sel1A_n <= '0';
  171           ElsIf Address = 16#1B# Then
  172              Sel1B_n <= '0';
  173           ElsIf Address = 16#1C# Then
  174              Sel1C_n <= '0';
  175           ElsIf Address = 16#1D# Then
  176              Sel1D_n <= '0';
  177           ElsIf Address = 16#1E# Then
  178              Sel1E_n <= '0';
  179           ElsIf Address = 16#1F# Then
  180              Sel1F_n <= '0';
  181           ElsIf Address = 16#20# Then
  182              Sel20_n <= '0';
  183           ElsIf Address = 16#21# Then
  184              Sel21_n <= '0';
  185           ElsIf Address = 16#22# Then
  186              Sel22_n <= '0';
  187           ElsIf Address = 16#23# Then
  188              Sel23_n <= '0';
  189           ElsIf Address = 16#24# Then
  190              Sel24_n <= '0';
  191           ElsIf Address = 16#25# Then
  192              Sel25_n <= '0';
  193           ElsIf Address = 16#26# Then
  194              Sel26_n <= '0';
  195           ElsIf Address = 16#27# Then
  196              Sel27_n <= '0';
  197           ElsIf Address = 16#28# Then
  198              Sel28_n <= '0';
  199           ElsIf Address = 16#29# Then
  200              Sel29_n <= '0';
  201           ElsIf Address = 16#2A# Then
  202              Sel2A_n <= '0';
  203           ElsIf Address = 16#2B# Then
  204              Sel2B_n <= '0';
  205           ElsIf Address = 16#2C# Then
  206              Sel2C_n <= '0';
  207           ElsIf Address = 16#2D# Then
  208              Sel2D_n <= '0';
  209  
  210           ElsIf Address = 16#3F# Then  -- Reg3F is register reading spare inputs
  211              Sel3F_n <= '0';
  212          End If;
  213        End If;
  214     End Process;
  215  end architecture a0 ; -- of AddressDecoder
  216  
  217