Generated by EASE/HDL for peterj on Mon Jul 02 10:55:31 2007

Documentation for architecture MROD_X_Out/TTC_DataMux/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'TTC_DataMux.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'TTC_DataMux' :
    5  -- 
    6  --   port(
    7  --     Adr   : in     std_logic;
    8  --     D_TTC : out    std_logic_vector(31 downto 0);
    9  --     EV_BC : in     std_logic_vector(24 downto 0);
   10  --     TT    : in     std_logic_vector(7 downto 0));
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of TTC_DataMux is
   15  
   16  BEGIN
   17     Process (Adr, TT, EV_BC)
   18     Begin
   19        If Adr = '0' Then
   20           D_TTC(24 Downto 0) <= EV_BC;
   21           D_TTC(31 Downto 25) <= (Others => '0');
   22        Else
   23           D_TTC(7 Downto 0) <= TT;
   24           D_TTC(31 Downto 8) <= (Others => '0');
   25        End If;
   26     End Process;
   27  end architecture a0 ; -- of TTC_DataMux
   28