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MROD_X_Out

Shift_In

Documentation for architecture MROD_X_Out/Shift_In/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Shift_In'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Bits :  positive := 10);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     Q     : out    std_logic_vector(Bits-1 downto 0);
   14  --     Rst_n : in     std_logic;
   15  --     SerIn : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of Shift_In is
   20  begin
   21     Process (Clk, Rst_n)
   22        Variable Q_Int: Std_Logic_Vector(Bits-1 downto 0);
   23     Begin
   24        If Rst_n = '0' Then
   25           Q_Int := (Others => '0');
   26        ElsIf Rising_Edge(Clk) Then
   27           For I In 0 To Bits - 2 Loop
   28              Q_Int(I) := Q_Int(I+1);
   29           End Loop;
   30           Q_Int(Bits - 1) := SerIn;
   31        End If;
   32        Q <= Q_Int;
   33     End Process;
   34  end architecture a0 ; -- of Shift_In
   35