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MROD_X_Out

Reg1Mux

Documentation for architecture MROD_X_Out/Reg1Mux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Reg1Mux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     BAR             : in     std_logic_vector(7 downto 0);
   11  --     InVME64xCrate_n : in     std_logic;
   12  --     Reg1d           : out    std_logic_vector(31 downto 0);
   13  --     VME_IRQ_n       : in     std_logic_vector(7 downto 1));
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of Reg1Mux is
   18  
   19  BEGIN
   20     Process(BAR, InVME64xCrate_n, VME_IRQ_n)
   21     Begin
   22        Reg1d(31 Downto 25) <= (Others => '0');
   23        Reg1d(24) <= InVME64xCrate_n;
   24        Reg1d(23 Downto 16) <= BAR;
   25        Reg1d(18 Downto 8) <= (Others => '0');
   26        Reg1d(7 Downto 1) <= NOT VME_IRQ_n;
   27        Reg1d(0) <= '0';
   28      End Process;
   29  end architecture a0 ; -- of Reg1Mux
   30