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MROD_X_Out

OutpDataMuxOE

Documentation for architecture MROD_X_Out/OutpDataMuxOE/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'OutpDataMuxOE'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     DENO0_n         : in     std_logic;
   11  --     DENO1_n         : in     std_logic;
   12  --     MS0_n           : in     std_logic;
   13  --     MS1_n           : in     std_logic;
   14  --     MS2_n           : in     std_logic;
   15  --     OE0_n           : out    std_logic;
   16  --     OE1_n           : out    std_logic;
   17  --     SharcRd_n       : in     std_logic;
   18  --     VMEInternalRd_n : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of OutpDataMuxOE is
   23  
   24  BEGIN
   25     Process (VMEInternalRd_n, SharcRd_n, MS0_n, MS1_n, MS2_n, DENO0_n, DENO1_n)
   26     Begin
   27        OE0_n <= '1';
   28        OE1_n <= '1';
   29        If VMEInternalRd_n = '0' Then
   30           OE0_n <= DENO0_n;
   31           OE1_n <= DENO1_n;
   32        --Note MS0_n and MS1_n are needed to distinghuish between a VMEbus acces to
   33        --the SHARC (ShracRd_n is also '0') and a Sharc Access to the FPGA.
   34        ElsIf SharcRd_n = '0' And (MS0_n = '0' Or MS1_n = '0' Or MS2_n = '0') Then
   35           OE0_n <= '0';
   36           OE1_n <= '0';
   37        End If;
   38     End Process;
   39  end architecture a0 ; -- of OutpDataMuxOE
   40