Generated by EASE/HDL for peterj on Mon Jul 02 10:55:28 2007
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Documentation for architecture MROD_X_Out/Low/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Low'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     O : out    std_logic_vector(n-1 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of Low is
   17  
   18  BEGIN
   19  
   20    O <= (Others => '0');
   21  
   22  end architecture a0 ; -- of Low
   23