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MROD_X_Out

Tri_Sharc

Documentation for architecture MROD_X_Out/Tri_Sharc/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Tri_Sharc'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     LocA     : in     std_logic_vector(63 downto 0);
   11  --     Oe_n     : in     std_logic;
   12  --     RdIn_n   : in     std_logic;
   13  --     Rd_n     : out    std_logic;
   14  --     SharcAdr : out    std_logic_vector(22 downto 0);
   15  --     WrIn_n   : in     std_logic;
   16  --     Wr_n     : out    std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of Tri_Sharc is
   21  
   22  begin
   23     Process (LocA, RdIn_n, WrIn_n, Oe_n)
   24     Begin
   25     --The Sharc address bus is 32-bit word oriented.
   26     --The VME bus is byte oriented.
   27     --The 32-bit word addresses of the Sharc Range to 0x000FFFFF. So Address lines A[19..0]
   28     --need to be passed to the Sharc. The M field A[22..20] should be driven "000" for 
   29     --asynchronous accesses. See SHARC Technical Specification Page 7-9.
   30     --Sharc A[19..0] corresponds to Byte Addresses LocA[21..2].
   31        If Oe_n = '0' Then
   32           SharcAdr(22 Downto 20) <= (Others => '0');
   33           SharcAdr(19 Downto 0) <= LocA(21 downto 2);
   34           Rd_n <= RdIn_n;
   35           Wr_n <= WrIn_n;
   36        Else
   37           SharcAdr <= (Others => 'Z');
   38           Rd_n <= 'Z';
   39           Wr_n <= 'Z';
   40        End If;
   41     End Process;
   42  end architecture a0 ; -- of Tri_Sharc
   43