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MROD_X_Out

Reg1

Documentation for architecture MROD_X_Out/Reg1/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Reg1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     D     : in     std_logic;
   12  --     Q     : out    std_logic;
   13  --     Rst_n : in     std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of Reg1 is
   18  
   19  BEGIN
   20     Process (Clk, Rst_n)
   21     Begin
   22        If Rst_n = '0' Then
   23           Q <= '0';
   24        ElsIf Rising_Edge(Clk) Then
   25           Q <= D;
   26        End If;    
   27     End Process;
   28  end architecture a0 ; -- of Reg1
   29