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MROD_X_Out

OutpDataMux

Documentation for architecture MROD_X_Out/OutpDataMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'OutpDataMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D               : out    std_logic_vector(31 downto 0);
   11  --     D_Regs          : in     std_logic_vector(31 downto 0);
   12  --     D_Spy           : in     std_logic_vector(31 downto 0);
   13  --     D_TTC           : in     std_logic_vector(31 downto 0);
   14  --     D_VMEInternal   : in     std_logic_vector(31 downto 0);
   15  --     MS0_n           : in     std_logic;
   16  --     MS1_n           : in     std_logic;
   17  --     MS2_n           : in     std_logic;
   18  --     VMEInternalRd_n : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of OutpDataMux is
   23  
   24  BEGIN
   25     Process (MS0_n, MS1_n, MS2_n, VMEInternalRd_n,
   26              D_TTC, D_Spy, D_Regs, D_VMEInternal)
   27     -- Watch out! The D-Fifo bus is passed by default because
   28     -- this one has to be fast! We don't have to wait for MS1_n
   29     -- to get active.
   30     -- At least for D_Fifo_EVBC but not for D_Fifo_TT.
   31     Begin
   32        If MS0_n = '0' Then
   33           D <= D_Regs;
   34        ElsIf MS1_n = '0' Then
   35           D <= D_TTC;
   36        ElsIf MS2_n = '0' Then
   37           D <= D_Spy;
   38        ElsIf VMEInternalRd_n = '0' Then
   39           D <= D_VMEInternal;
   40        Else
   41           D <= D_TTC;
   42        End If;
   43     End Process;
   44  
   45  end architecture a0 ; -- of OutpDataMux
   46