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MROD_X_Out

Dec_CR_CSR

Documentation for architecture MROD_X_Out/Dec_CR_CSR/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Dec_CR_CSR'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A24         : in     std_logic;
   11  --     Adr         : in     std_logic_vector(23 downto 0);
   12  --     BAR         : in     std_logic_vector(7 downto 0);
   13  --     CR_CSR      : in     std_logic;
   14  --     Clk         : in     std_logic;
   15  --     Cs_CR_CSR_n : out    std_logic;
   16  --     DECODE      : in     std_logic;
   17  --     DSB         : in     std_logic;
   18  --     Er_CR_CSR_n : out    std_logic;
   19  --     Rst_n       : in     std_logic;
   20  --     WRITE_n     : in     std_logic);
   21  -- 
   22  -- EASE/HDL end ----------------------------------------------------------------
   23  
   24  architecture a0 of Dec_CR_CSR is
   25     Signal InternalDecode: Boolean;
   26     Signal Acces_CSR: Boolean;
   27     Signal Acces_CR: Boolean;
   28  begin
   29  
   30     --This part only decodes the VME64x Standard defined-CR 0x00000-0x00FFF
   31     --and VME64x Standard defined-CSR space 0x7FC00-0x7FFFF.
   32     --If one of these address ranges is decoded then Cs_CrR_CSR_n is asserted.
   33     --Note that CR is Read Only. A write to CR should result in a BERR_n.
   34     --Therefore Er_CR_CSR_n is asserted as well in this case.
   35     --Note 2: Further decoding of the CR and CSR space is done locally in
   36     --the CR_CSR entity.
   37  
   38     InternalDecode <= (A24 = '1' And CR_CSR = '1' And (BAR(7 Downto 3) = Adr(23 Downto 19)));
   39  
   40     --Defined Config ROM 0x00000 - 0x00FFF
   41     Acces_CR <= InternalDecode And (Unsigned(Adr(18 Downto 0)) < 16#1000#);
   42  
   43     --Defined CSR 0x7FC00 - 0x7FFFF
   44     Acces_CSR <= InternalDecode And (Unsigned(Adr(18 Downto 0)) >= 16#7FC00#);
   45  
   46     Process (Clk, Rst_n)
   47     Begin
   48        If Rst_n = '0' Then
   49           Er_CR_CSR_n <= '1';
   50        ElsIf Rising_Edge(Clk) Then
   51  --   Process (DSB, Acces_CR, WRITE_n)
   52  --   Begin
   53          --Check each Data Phase for a correct transfer (CR is Read Only)
   54           If DSB = '1' And Acces_CR = True And WRITE_n = '0' Then
   55              Er_CR_CSR_n <= '0';
   56           Else
   57              Er_CR_CSR_n <= '1';
   58           End If;
   59        End If;
   60     End Process;
   61  
   62  
   63     Process (Clk, Rst_n)
   64     Begin
   65        If Rst_n = '0' Then
   66           Cs_CR_CSR_n <= '1';
   67        ElsIf Rising_Edge(Clk) Then
   68           --the Chip Select signal is continuously updated but as soon as the
   69           --DECODE signal arrives the result is holded for the duration of DECODE
   70           --Note this covers the complete Address Phase (AS_n)
   71           If DECODE = '0' Then
   72              If Acces_CR = True Or Acces_CSR = True Then
   73                 Cs_CR_CSR_n <= '0';
   74              Else
   75                 Cs_CR_CSR_n <= '1';
   76              End If;
   77           End If;
   78        End If;
   79     End Process;
   80  end architecture a0 ; -- of Dec_CR_CSR
   81