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MROD_X_Out

Tri1

Documentation for architecture MROD_X_Out/Tri1/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Tri1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     I    : in     std_logic;
   11  --     O    : out    std_logic;
   12  --     Oe_n : in     std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of Tri1 is
   17  
   18  begin
   19     Process (I, Oe_n)
   20     Begin
   21        If Oe_n = '0' Then
   22           O <= I;
   23        Else
   24           O <= 'Z';
   25        End If;
   26     End Process;
   27  end architecture a0 ; -- of Tri1
   28