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MROD_X_Out

Reg

Documentation for architecture MROD_X_Out/Reg/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Reg'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_vector(n-1 downto 0);
   14  --     Q     : out    std_logic_vector(n-1 downto 0);
   15  --     Rst_n : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of Reg is
   20  
   21  BEGIN
   22     Process (Clk, Rst_n)
   23     Begin
   24        If Rst_n = '0' Then
   25           Q <= (others => '0');
   26        ElsIf Rising_Edge(Clk) Then
   27           Q <= D;
   28        End If;    
   29     End Process;
   30  end architecture a0 ; -- of Reg
   31