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MROD_X_Out

FPGA_InternalDataMux

Documentation for architecture MROD_X_Out/FPGA_InternalDataMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FPGA_InternalDataMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     CR_CSR_D    : in     std_logic_vector(7 downto 0);
   11  --     CS_CR_CSR_n : in     std_logic;
   12  --     CS_IRQ_n    : in     std_logic;
   13  --     IRQ_Data    : in     std_logic_vector(7 downto 0);
   14  --     Oe_n        : out    std_logic;
   15  --     VME_D       : out    std_logic_vector(31 downto 0));
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of FPGA_InternalDataMux is
   20  
   21  begin
   22     Process (CR_CSR_D, IRQ_Data,
   23              CS_CR_CSR_n, CS_IRQ_n)
   24     Begin
   25        VME_D <= (Others => '0');
   26        If CS_CR_CSR_n = '0' Then
   27           VME_D(7 Downto 0) <= CR_CSR_D;
   28           Oe_n <= '0';
   29        ElsIf CS_IRQ_n = '0' Then
   30           VME_D(7 Downto 0) <= IRQ_Data;
   31           Oe_n <= '0';
   32        Else
   33           Oe_n <= '1';
   34        End If;
   35     End Process;
   36  end architecture a0 ; -- of FPGA_InternalDataMux
   37