Generated by EASE/HDL for peterj on Mon Jul 02 10:55:25 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'BitSet_Clr'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- BERR_n : in std_logic; 11 -- CRAM_Owned : in std_logic; 12 -- Clk : in std_logic; 13 -- Cs_BitClr_n : in std_logic; 14 -- Cs_BitSet_n : in std_logic; 15 -- D : in std_logic_vector(7 downto 0); 16 -- JustBeforeDTACK : in std_logic; 17 -- ModuleFail : in std_logic; 18 -- Q : out std_logic_vector(7 downto 0); 19 -- R_W_n : in std_logic; 20 -- Rst_n : in std_logic); 21 -- 22 -- EASE/HDL end ---------------------------------------------------------------- 23 24 architecture a0 of BitSet_Clr is 25 26 begin 27 Process (Clk, Rst_n) 28 Begin 29 If Rst_n = '0' Then 30 Q <= (Others => '0'); 31 ElsIf Rising_Edge (Clk) Then 32 33 --Set the "Module Failed" as defined in 34 --VME64 and VME64x Table 10-6 and Table 10-7 35 If ModuleFail = '1' Then 36 Q(5) <= '1'; 37 38 --Set the "Module issued BERR_n" as defined in 39 --VME64x Table 10-6 and Table 10-7 40 ElsIf BERR_n = '0' Then 41 Q(3) <= '1'; 42 43 --Set the "CRAM Owned" as defined in 44 --VME64x Table 10-6 and Table 10-7 45 ElsIf CRAM_Owned = '1' Then 46 Q(2) <= '1'; 47 48 -- Access the Bit Set Register 49 ElsIf Cs_BitSet_n = '0' And R_W_n = '0' And JustBeforeDTACK = '1' Then 50 For I in 0 To 7 Loop 51 If D(I) = '1' Then 52 Q(I) <= '1'; 53 End If; 54 End Loop; 55 -- Access the Bit Clear Register 56 ElsIf Cs_BitClr_n = '0' And R_W_n = '0' And JustBeforeDTACK = '1' Then 57 For I in 0 To 7 Loop 58 If D(I) = '1' Then 59 Q(I) <= '0'; 60 End If; 61 End Loop; 62 End If; 63 End If; 64 End Process; 65 end architecture a0 ; -- of BitSet_Clr 66