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MROD_X_Out

AckGen

Documentation for architecture MROD_X_Out/AckGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AckGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Ack        : out    std_logic;
   11  --     MS3_n      : in     std_logic;
   12  --     S_LINKFull : in     std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of AckGen is
   17  
   18  BEGIN
   19     Process (MS3_n, S_LINKFull)
   20     Begin
   21        If MS3_n = '0' And S_LINKFull = '1' Then
   22              Ack <= '0';
   23           Else
   24              Ack <= '1';
   25        End If; 
   26     End Process;
   27  end architecture a0 ; -- of AckGen
   28