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MROD_X_Out

Tri

Documentation for architecture MROD_X_Out/Tri/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Tri'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     I    : in     std_logic_vector(n-1 downto 0);
   13  --     O    : out    std_logic_vector(n-1 downto 0);
   14  --     Oe_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Tri is
   19  
   20  begin
   21     Process (I, Oe_n)
   22     Begin
   23        If Oe_n = '0' Then
   24           O <= I;
   25        Else
   26           O <= (Others => 'Z');
   27        End If;
   28     End Process;
   29  end architecture a0 ; -- of Tri
   30