Generated by EASE/HDL for peterj on Mon Jul 02 10:55:28 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a0' of 'LFF_Logic. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'LFF_Logic' : 5 -- 6 -- port( 7 -- I : in std_logic; 8 -- LFF_n : in std_logic; 9 -- O : out std_logic); 10 -- 11 -- EASE/HDL end ---------------------------------------------------------------- 12 13 architecture a0 of LFF_Logic is 14 15 begin 16 Process (LFF_n, I) 17 Begin 18 If LFF_n = '1' Then 19 O <= I; 20 Else 21 O <= '1'; 22 End If; 23 End Process; 24 end architecture a0 ; -- of LFF_Logic 25