Back

Index

MROD_X_Out

BitCount

Documentation for architecture MROD_X_Out/BitCount/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'BitCount'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Bits  :  positive := 10;
   11  --     BitsU :  positive := 4);
   12  --   port(
   13  --     Clk     : in     std_logic;
   14  --     Is_Bits : out    std_logic;
   15  --     Rst_n   : in     std_logic;
   16  --     Start   : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of BitCount is
   21  BEGIN
   22     Process (Clk, Rst_n)
   23        Variable Cnt: Unsigned(BitsU - 1 Downto 0);
   24     Begin
   25        If Rst_n = '0' Then
   26           Cnt := To_Unsigned(Bits,BitsU);
   27        ElsIf Rising_Edge(Clk) Then
   28           If To_Integer(Cnt) =  Bits Then
   29              If Start = '1' Then
   30                 Cnt := (Others => '0');
   31              End If;
   32           Else
   33              Cnt := Cnt + 1;
   34           End If;
   35        End If;
   36  
   37        If To_Integer(Cnt) = Bits Then
   38           Is_Bits <= '1';
   39        Else
   40           Is_Bits <= '0';
   41        End If;
   42     End Process;
   43  end architecture a0 ; -- of BitCount
   44