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MROD_X_Out

SHARC_Selector

Documentation for architecture MROD_X_Out/SHARC_Selector/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'SHARC_Selector'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     CS_n      : in     std_logic;
   11  --     CSa_n     : out    std_logic;
   12  --     CSb_n     : out    std_logic;
   13  --     S_Redy    : out    std_logic;
   14  --     S_Redy_a  : in     std_logic;
   15  --     S_Redy_b  : in     std_logic;
   16  --     Sel_B_A_n : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of SHARC_Selector is
   21  
   22  BEGIN
   23     Process (Sel_B_A_n, CS_n, S_Redy_a, S_Redy_b)
   24     Begin
   25        If Sel_B_A_n = '0' Then
   26           CSa_n <= CS_n;
   27           CSb_n <= '1';
   28           S_Redy <= S_Redy_a;
   29        Else
   30           CSa_n <= '1';
   31           CSb_n <= CS_n;
   32           S_Redy <= S_Redy_b;
   33        End If;
   34     End Process;
   35  end architecture a0 ; -- of SHARC_Selector
   36