Documentation for architecture MROD_X_Out/LevelMatch/a0
VHDL Contents
1 architecture a0 of LevelMatch is
19
20 begin
21 Process (Clk, Rst_n)
25 Begin
26 If Rst_n = '0' Then
27 LvlMatch <= '0';
28 ElsIf Rising_Edge(Clk) Then
29 Case VME_IRQ_n Is
30 When "0111111" =>
31 If Adr = "111" Then
32 LvlMatch <= '1';
33 Else
34 LvlMatch <= '0';
35 End If;
36 When "1011111" =>
37 If Adr = "110" Then
38 LvlMatch <= '1';
39 Else
40 LvlMatch <= '0';
41 End If;
42 When "1101111" =>
43 If Adr = "101" Then
44 LvlMatch <= '1';
45 Else
46 LvlMatch <= '0';
47 End If;
48 When "1110111" =>
49 If Adr = "100" Then
50 LvlMatch <= '1';
51 Else
52 LvlMatch <= '0';
53 End If;
54 When "1111011" =>
55 If Adr = "011" Then
56 LvlMatch <= '1';
57 Else
58 LvlMatch <= '0';
59 End If;
60 When "1111101" =>
61 If Adr = "010" Then
62 LvlMatch <= '1';
63 Else
64 LvlMatch <= '0';
65 End If;
66 When "1111110" =>
67 If Adr = "001" Then
68 LvlMatch <= '1';
69 Else
70 LvlMatch <= '0';
71 End If;
72 When Others =>
73 LvlMatch <= '0';
74 End Case;
75 End If;
76 End Process;
77 end architecture a0 ;