Generated by EASE/HDL for peterj on Mon Jul 02 10:55:26 2007

Documentation for architecture MROD_X_Out/DataSink/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DataSink'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     OutputFileName   :  String := "DataSink.out";
   11  --     OutpFifoDumpName :  String := "OutpFifoDump.out";
   12  --     MS0_Wait         :  natural := 3;
   13  --     MS1_Wait         :  natural := 1;
   14  --     MS3_Wait         :  natural := 3;
   15  --     MS2_Wait         :  natural := 1;
   16  --     SpyFileName      :  String := "SpyFifoDump.out");
   17  --   port(
   18  --     Adr   : in     std_logic_vector(31 downto 0);
   19  --     Clk   : in     std_logic;
   20  --     Data  : in     std_logic_vector(31 downto 0);
   21  --     MS0_n : in     std_logic;
   22  --     MS1_n : in     std_logic;
   23  --     MS2_n : in     std_logic;
   24  --     MS3_n : in     std_logic;
   25  --     Rd_n  : in     std_logic;
   26  --     Wr_n  : in     std_logic);
   27  -- 
   28  -- EASE/HDL end ----------------------------------------------------------------
   29  
   30  architecture a0 of DataSink is
   31  
   32  BEGIN
   33     Process (Clk, MS0_n, MS1_n, MS3_n, Rd_n, Wr_n)
   34        File OutpFile: ASCII_Text Open Write_Mode Is OutputFileName;
   35        File SpyFile: ASCII_Text Open Write_Mode Is SpyFileName;
   36        File DumpFile: ASCII_Text Open Write_Mode Is OutpFifoDumpName;
   37        Variable Hex_Str: String(1 To MAX_STRING_LEN);
   38        Variable Line_No: Integer;
   39        Variable FirstLine: Boolean := True;
   40        Variable WaitCycleMS1_n: Natural := 0;
   41        Variable WaitCycleMS2_n: Natural := 0;
   42        Variable WaitCycleMS3_n: Natural := 0;
   43     Begin   
   44        If FirstLine then 
   45           fprint(OutpFile,"Time          Cycle Type  Data Word  Adr   Data\n");
   46           Line_No := 0;
   47           FirstLine := False;
   48        End if;
   49  
   50        If (Not FirstLine) Then
   51           If MS0_n = '0' And Rising_Edge(Rd_n) Then
   52  --            fprint(OutpFile,"%s  Config Rd              %s %s\n", To_String(Now)  , To_HexString(Adr), To_HexString(Data));
   53              fprint(OutpFile,"%s  Config Rd              %s %s\n",
   54                     To_String(Now),
   55                     To_String(To_Bitvector(Adr(31 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
   56                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   57                     );
   58  
   59              If Adr(7 Downto 0) = Std_Logic_Vector(To_Unsigned(16#5D#,8)) Then
   60                 fprint(SpyFile,"Event_Length                %s\n",
   61                        To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   62                        );
   63              End If;
   64  
   65           ElsIf MS0_n = '0' And Rising_Edge(Wr_n) Then
   66  --            fprint(OutpFile,"%s  Config Wr              %s %s\n", To_String(Now)  , To_HexString(Adr), To_HexString(Data));
   67              fprint(OutpFile,"%s  Config Wr              %s %s\n",
   68                     To_String(Now),
   69                     To_String(To_Bitvector(Adr(31 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
   70                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   71                     );
   72           ElsIf Rising_Edge(Clk) And MS1_n = '0' And Rd_n = '0' And WaitCycleMS1_n = MS1_Wait Then
   73  --            fprint(OutpFile,"%s  OutpFifo Rd %s         %s\n", To_String(Now) , To_String(Line_No,"%-8d") , To_HexString(Data));
   74              fprint(OutpFile,"%s  OutpFifo Rd %s         %s\n",
   75                     To_String(Now),
   76                     To_String(Line_No,"%-8d"),
   77                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   78                     );
   79  
   80  --            fprint(DumpFile,"        %s\n", To_HexString(Data));
   81              fprint(DumpFile,"        %s\n",
   82                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   83                     );
   84              Line_No := Line_No + 1;
   85           ElsIf Rising_Edge(Clk) And MS1_n = '0' And Wr_n = '0' And WaitCycleMS1_n = MS1_Wait Then
   86              fprint(OutpFile,"%s  OutpFifo Write????\n", To_String(Now));
   87  
   88           ElsIf Rising_Edge(Clk) And MS2_n = '0' And Rd_n = '0' And WaitCycleMS2_n = MS2_Wait Then
   89  --            fprint(SpyFile,"        %s\n", To_HexString(Data));
   90              fprint(SpyFile,"        %s\n",
   91                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   92                     );
   93              Line_No := Line_No + 1;
   94           ElsIf Rising_Edge(Clk) And MS2_n = '0' And Wr_n = '0' And WaitCycleMS2_n = MS2_Wait Then
   95              fprint(SpyFile,"%s  SpyFifo Write????\n", To_String(Now));
   96  
   97           ElsIf Rising_Edge(Clk) And MS3_n = '0' And Rd_n = '0' And WaitCycleMS3_n = MS3_Wait Then
   98  --            fprint(OutpFile,"%s  S-LINK RD              %s %s\n", To_String(Now)  , To_HexString(Adr), To_HexString(Data));
   99              fprint(OutpFile,"%s  S-LINK RD              %s %s\n",
  100                     To_String(Now),
  101                     To_String(To_Bitvector(Adr(31 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
  102                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
  103                     );
  104           ElsIf Rising_Edge(Clk) And MS3_n = '0' And Wr_n = '0' And WaitCycleMS3_n = MS3_Wait Then
  105  --            fprint(OutpFile,"%s  S_LINK WR              %s %s\n", To_String(Now)  , To_HexString(Adr), To_HexString(Data));
  106              fprint(OutpFile,"%s  S_LINK WR              %s %s\n",
  107                     To_String(Now),
  108                     To_String(To_Bitvector(Adr(31 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
  109                     To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
  110                     );
  111           End If;
  112  
  113           If Rising_Edge(Clk) Then
  114              If WaitCycleMS1_n = MS1_Wait Then
  115                 WaitCycleMS1_n := 0;
  116              ElsIf MS1_n = '0' Then
  117                 WaitCycleMS1_n := WaitCycleMS1_n + 1;
  118              Else
  119                 WaitCycleMS1_n := 0;
  120              End If;
  121  
  122              If WaitCycleMS2_n = MS2_Wait Then
  123                 WaitCycleMS2_n := 0;
  124              ElsIf MS2_n = '0' Then
  125                 WaitCycleMS2_n := WaitCycleMS2_n + 1;
  126              Else
  127                 WaitCycleMS2_n := 0;
  128              End If;
  129  
  130              If WaitCycleMS3_n = MS3_Wait Then
  131                 WaitCycleMS3_n := 0;
  132              ElsIf MS3_n = '0' Then
  133                 WaitCycleMS3_n := WaitCycleMS3_n + 1;
  134              Else
  135                 WaitCycleMS3_n := 0;
  136              End If;
  137           End If;
  138        End if;
  139  
  140     End Process;
  141  end architecture a0 ; -- of DataSink
  142