Back

Index

MROD_X_Out

BE_Decode

Documentation for architecture MROD_X_Out/BE_Decode/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'BE_Decode'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A1      : in     std_logic;
   11  --     Byte8   : out    std_logic;
   12  --     Clk     : in     std_logic;
   13  --     D64     : in     std_logic;
   14  --     DBE_n   : out    std_logic_vector(3 downto 0);
   15  --     DS0_n   : in     std_logic;
   16  --     DS1_n   : in     std_logic;
   17  --     Double  : out    std_logic;
   18  --     IACK_n  : in     std_logic;
   19  --     LWORD_n : in     std_logic;
   20  --     Quad    : out    std_logic;
   21  --     Rst_n   : in     std_logic;
   22  --     SWDEN_n : out    std_logic;
   23  --     Single  : out    std_logic);
   24  -- 
   25  -- EASE/HDL end ----------------------------------------------------------------
   26  
   27  architecture a0 of BE_Decode is
   28     Signal DBE_Int_n: Std_Logic_Vector(3 Downto 0);
   29     Signal SWDEN_Int_n: Std_Logic;
   30  BEGIN
   31     --NOTE: DBE_n and SWDEN_n are Registered. Single, Double, Quad and Byte8 are not!
   32     --Single, Double, Quad and Byte8 can be used in the decoder sections and therefore
   33     --need to be present as fast as posible.
   34  
   35     Process (Clk, Rst_n)
   36     Begin
   37        If Rst_n = '0' Then
   38           DBE_n <= (Others => '1');
   39           SWDEN_n <= '1';
   40        ElsIf Rising_Edge(Clk) Then
   41           DBE_n <= DBE_Int_n;
   42           SWDEN_n <= SWDEN_Int_n;
   43        End If;
   44     End Process;
   45  
   46     Process (DS1_n, DS0_n, LWORD_n, IACK_n, A1, D64)
   47     Begin
   48        Single <= '0';
   49        Double <= '0';
   50        Quad <= '0';
   51        Byte8 <= '0';
   52  
   53  
   54        If IACK_n = '1' Then
   55           ------------------------
   56           --Address Only Transfers
   57           ------------------------
   58           If DS1_n = '1' And DS0_n = '1' Then
   59           -- Address Only
   60              DBE_Int_n (0) <= '1';
   61              DBE_Int_n (1) <= '1';
   62              DBE_Int_n (2) <= '1';
   63              DBE_Int_n (3) <= '1';
   64              SWDEN_Int_n <= '1';
   65              -- No need for Single, Double, Quad and Byte8
   66              -- to increment the address counter
   67  
   68              ------------------------
   69              --Quad Byte Transfers:
   70              ------------------------
   71              ElsIf D64 = '0' And LWORD_n = '0' And A1 = '0' And DS1_n = '0' And DS0_n = '0' Then
   72              -- Byte 0-3 Group / Quad Byte Transfer
   73              DBE_Int_n (0) <= '0';
   74              DBE_Int_n (1) <= '0';
   75              DBE_Int_n (2) <= '0';
   76              DBE_Int_n (3) <= '0';
   77              SWDEN_Int_n <= '1';
   78  
   79              Quad <= '1';
   80           ------------------------
   81           --Unaligned Transfers:
   82           ------------------------
   83           ElsIf D64 = '0' And LWORD_n = '0' And A1 = '0' And DS1_n = '0' And DS0_n = '1' Then
   84           -- Byte 0-3 Group / 3 Byte Unaligned Transfer Byte 0-2
   85              DBE_Int_n (0) <= '0';
   86              DBE_Int_n (1) <= '0';
   87              DBE_Int_n (2) <= '0';
   88              DBE_Int_n (3) <= '1';
   89              SWDEN_Int_n <= '1';
   90  
   91           -- UAT doesn't exist in Block Transfer Mode so Single, Double, Quad and Byte8 are not needed
   92           -- to increment the address counter
   93           -- UAT_0_1_2 <= '1';
   94  
   95           ElsIf D64 = '0' And LWORD_n = '0' And A1 = '0' And DS1_n = '1' And DS0_n = '0' Then
   96           -- Byte 0-3 Group / 3 Byte Unaligned Transfer Byte 1-3
   97              DBE_Int_n (0) <= '1';
   98              DBE_Int_n (1) <= '0';
   99              DBE_Int_n (2) <= '0';
  100              DBE_Int_n (3) <= '0';
  101              SWDEN_Int_n <= '1';
  102  
  103           -- UAT doesn't exist in Block Transfer Mode so Single, Double, Quad and Byte8 are not needed
  104           -- to increment the address counter
  105           -- UAT_1_2_3 <= '1';
  106           ElsIf D64 = '0' And LWORD_n = '0' And A1 = '1' And DS1_n = '0' And DS0_n = '0' Then
  107           -- Byte 0-3 Group / 2 Byte Unaligned Transfer Byte 1-2
  108              DBE_Int_n (0) <= '1';
  109              DBE_Int_n (1) <= '0';
  110              DBE_Int_n (2) <= '0';
  111              DBE_Int_n (3) <= '1';
  112              SWDEN_Int_n <= '1';
  113  
  114           -- UAT doesn't exist in Block Transfer Mode so Single, Double, Quad and Byte8 are not needed
  115           -- to increment the address counter
  116           -- UAT_1_2 <= '1';
  117  
  118           ElsIf D64 = '0' And LWORD_n = '0' And A1 = '1' And (DS1_n = '1' Or DS1_n = '0') Then
  119           -- Illegal (Rule 2.1a)
  120              DBE_Int_n (0) <= '1';
  121              DBE_Int_n (1) <= '1';
  122              DBE_Int_n (2) <= '1';
  123              DBE_Int_n (3) <= '1';
  124              SWDEN_Int_n <= '1';
  125           ------------------------
  126           --Double Byte Transfers:
  127           ------------------------
  128           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '0' And DS1_n = '0' And DS0_n = '0' Then
  129           -- Byte 0-3 Group / Double Byte Transfer Byte 0-1; Note the SWAP DBE_Int_n(0-1) -> DBE_Int_n (2-3)
  130              DBE_Int_n (0) <= '0';
  131              DBE_Int_n (1) <= '0';
  132              DBE_Int_n (2) <= '1';
  133              DBE_Int_n (3) <= '1';
  134              SWDEN_Int_n <= '0';
  135  
  136              Double <= '1';
  137  
  138           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '1' And DS1_n = '0' And DS0_n = '0' Then
  139           -- Byte 0-3 Group / Double Byte Transfer Byte 2-3
  140              DBE_Int_n (0) <= '1';
  141              DBE_Int_n (1) <= '1';
  142              DBE_Int_n (2) <= '0';
  143              DBE_Int_n (3) <= '0';
  144              SWDEN_Int_n <= '1';
  145  
  146              Double <= '1';
  147           ------------------------
  148           --Single Byte Transfers:
  149           ------------------------
  150           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '0' And DS1_n = '0' And DS0_n = '1' Then
  151           -- Byte 0-3 Group / Single Byte Transfer Byte 0; Note the SWAP DBE_Int_n(0) -> DBE_Int_n (2)
  152              DBE_Int_n (0) <= '0';
  153              DBE_Int_n (1) <= '1';
  154              DBE_Int_n (2) <= '1';
  155              DBE_Int_n (3) <= '1';
  156              SWDEN_Int_n <= '0';
  157  
  158              Single <= '1';
  159  
  160           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '0' And DS1_n = '1' And DS0_n = '0' Then
  161           -- Byte 0-3 Group / Single Byte Transfer Byte 1; Note the SWAP DBE_Int_n(1) -> DBE_Int_n (3)
  162              DBE_Int_n (0) <= '1';
  163              DBE_Int_n (1) <= '0';
  164              DBE_Int_n (2) <= '1';
  165              DBE_Int_n (3) <= '1';
  166              SWDEN_Int_n <= '0';
  167  
  168              Single <= '1';
  169   
  170           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '1' And DS1_n = '0' And DS0_n = '1' Then
  171           -- Byte 0-3 Group / Single Byte Transfer Byte 2
  172              DBE_Int_n (0) <= '1';
  173              DBE_Int_n (1) <= '1';
  174              DBE_Int_n (2) <= '0';
  175              DBE_Int_n (3) <= '1';
  176              SWDEN_Int_n <= '1';
  177  
  178              Single <= '1';
  179  
  180           ElsIf D64 = '0' And LWORD_n = '1' And A1 = '1' And DS1_n = '1' And DS0_n = '0' Then
  181           -- Byte 0-3 Group / Single Byte Transfer Byte 3
  182              DBE_Int_n (0) <= '1';
  183              DBE_Int_n (1) <= '1';
  184              DBE_Int_n (2) <= '1';
  185              DBE_Int_n (3) <= '0';
  186              SWDEN_Int_n <= '1';
  187  
  188              Single <= '1';
  189  
  190           ------------------------
  191           --64 Bit Transfers:
  192           ------------------------
  193           ElsIf D64 = '1' And LWORD_n = '0' And A1 = '0' And DS1_n = '0' And DS0_n = '0' Then
  194           -- Byte 0-7 Group / 64 bit Transfer
  195           -- MBLT: A31-A24  A23-A16   A15-A8  A7-A1,LWORD*  D31-D24  D23-D16  D15-D8  D7-D0
  196           --        Byte0    Byte1    Byte2     Byte3       Byte4    Byte5    Byte6  Byte7
  197              DBE_Int_n (0) <= '0';
  198              DBE_Int_n (1) <= '0';
  199              DBE_Int_n (2) <= '0';
  200              DBE_Int_n (3) <= '0';
  201              SWDEN_Int_n <= '1';
  202  
  203              Byte8 <= '1';
  204  
  205           Else
  206           -- Illegal (Rule 2.69)
  207              DBE_Int_n (0) <= '1';
  208              DBE_Int_n (1) <= '1';
  209              DBE_Int_n (2) <= '1';
  210              DBE_Int_n (3) <= '1';
  211              SWDEN_Int_n <= '1';
  212           End If;
  213        Else
  214  
  215           --Interrupt Acknowledge Cycle
  216           --Note that A1 is not decoded since it is used to signal the IRQ Level
  217  
  218           -------------------------
  219           --Quad Byte Transfers D32:
  220           -------------------------
  221           If D64 = '0' And LWORD_n = '0' And DS1_n = '0' And DS0_n = '0' Then
  222           -- Byte 0-3 Group / Quad Byte Transfer
  223              DBE_Int_n (0) <= '0';
  224              DBE_Int_n (1) <= '0';
  225              DBE_Int_n (2) <= '0';
  226              DBE_Int_n (3) <= '0';
  227              SWDEN_Int_n <= '1';
  228  
  229              Quad <= '1';
  230           ---------------------------
  231           --Double Byte Transfers D16:
  232           ---------------------------
  233           ElsIf D64 = '0' And LWORD_n = '1' And DS1_n = '0' And DS0_n = '0' Then
  234           -- Byte 0-3 Group / Double Byte Transfer Byte 2-3
  235              DBE_Int_n (0) <= '1';
  236              DBE_Int_n (1) <= '1';
  237              DBE_Int_n (2) <= '0';
  238              DBE_Int_n (3) <= '0';
  239              SWDEN_Int_n <= '1';
  240  
  241              Double <= '1';
  242           ------------------------------
  243           --Single Byte Transfers D08(O):
  244           ------------------------------
  245           ElsIf D64 = '0' And LWORD_n = '1' And DS1_n = '1' And DS0_n = '0' Then
  246           -- Byte 0-3 Group / Single Byte Transfer Byte 3
  247              DBE_Int_n (0) <= '1';
  248              DBE_Int_n (1) <= '1';
  249              DBE_Int_n (2) <= '1';
  250              DBE_Int_n (3) <= '0';
  251              SWDEN_Int_n <= '1';
  252  
  253              Single <= '1';
  254  
  255           Else
  256           -- Illegal (Rule 2.69)
  257              DBE_Int_n (0) <= '1';
  258              DBE_Int_n (1) <= '1';
  259              DBE_Int_n (2) <= '1';
  260              DBE_Int_n (3) <= '1';
  261              SWDEN_Int_n <= '1';
  262           End If;
  263        End If;
  264  
  265     End Process;
  266  end architecture a0 ; -- of BE_Decode
  267