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MROD_X_Out

Zet

Documentation for architecture MROD_X_Out/Zet/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'Zet.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'Zet' :
    5  -- 
    6  --   port(
    7  --     p0 : out    std_logic);
    8  -- 
    9  -- EASE/HDL end ----------------------------------------------------------------
   10  
   11  architecture a0 of Zet is
   12  
   13  begin
   14     p0 <= 'Z';
   15  end architecture a0 ; -- of Zet
   16