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MROD_X_Out

Sharc_Sel

Documentation for architecture MROD_X_Out/Sharc_Sel/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Sharc_Sel'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr_Dec    : in     std_logic;
   11  --     Clk        : in     std_logic;
   12  --     Cs_Sharc_n : out    std_logic;
   13  --     DECODE     : in     std_logic;
   14  --     DSB        : in     std_logic;
   15  --     Er_Sharc_n : out    std_logic;
   16  --     Quad       : in     std_logic;
   17  --     Rst_n      : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of Sharc_Sel is
   22  
   23  BEGIN
   24     Process (Clk, Rst_n)
   25     Begin
   26        If Rst_n = '0' Then
   27           Er_Sharc_n <= '1';
   28        ElsIf Rising_Edge(Clk) Then
   29  --   Process (DSB, Adr_Dec, Quad)
   30  --   Begin
   31           --Check each Data Phase for a correct transfer (D32)
   32           If DSB = '1' And Adr_Dec = '1' And Quad = '0' Then
   33              Er_Sharc_n <= '0';
   34           Else
   35              Er_Sharc_n <= '1';
   36           End If;
   37        End If;
   38     End Process;
   39  
   40     Process (Clk, Rst_n)
   41     Begin
   42        If Rst_n = '0' Then
   43           Cs_Sharc_n <= '1';
   44        ElsIf Rising_Edge(Clk) Then
   45           --the Chip Select signal is continuously updated but as soon as the
   46           --DECODE signal arrives the result is holded for the duration of DECODE
   47           --Note this covers the complete Address Phase (AS_n)
   48           If DECODE = '0' Then
   49              If Adr_Dec = '1' Then
   50                 Cs_Sharc_n <= '0';
   51              Else
   52                 Cs_Sharc_n <= '1';
   53              End If;
   54           End If;
   55        End If;
   56     End Process;
   57  end architecture a0 ; -- of Sharc_Sel
   58