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MROD_X_Out

NC7SZ00

Documentation for architecture MROD_X_Out/NC7SZ00/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'NC7SZ00.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'NC7SZ00' :
    5  -- 
    6  --   port(
    7  --     A : in     std_logic;
    8  --     B : in     std_logic;
    9  --     O : out    std_logic);
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of NC7SZ00 is
   14  
   15  BEGIN
   16     O <= Not(A And B) After 2400 ps;
   17  end architecture a0 ; -- of NC7SZ00
   18