Generated by EASE/HDL for peterj on Mon Jul 02 10:55:28 2007

Documentation for architecture MROD_X_Out/LCellBuffer/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'LCellBuffer.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'LCellBuffer' :
    5  -- 
    6  --   port(
    7  --     I : in     std_logic;
    8  --     O : out    std_logic);
    9  -- 
   10  -- EASE/HDL end ----------------------------------------------------------------
   11  
   12  architecture a0 of LCellBuffer is
   13     Component LCELL_Extern
   14        Port (
   15           I : IN STD_LOGIC;
   16           O: OUT STD_LOGIC);
   17     End Component;
   18  
   19  BEGIN
   20     inst0: LCELL_Extern
   21        Port Map (
   22           I => I,
   23           O => O);
   24  end architecture a0 ; -- of LCellBuffer
   25