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MROD_X_Out

AndInv

Documentation for architecture MROD_X_Out/AndInv/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AndInv'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A  : in     std_logic;
   11  --     Bn : in     std_logic;
   12  --     O  : out    std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of AndInv is
   17  
   18  BEGIN
   19     O <= A And (NOT Bn);
   20  end architecture a0 ; -- of AndInv
   21