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MROD_X_Out

To_digital

Documentation for architecture MROD_X_Out/To_digital/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'To_digital'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     i0 : in     std_logic;
   11  --     i1 : in     std_logic;
   12  --     i2 : in     std_logic;
   13  --     i3 : in     std_logic;
   14  --     i4 : in     std_logic;
   15  --     i5 : in     std_logic;
   16  --     i6 : in     std_logic;
   17  --     o0 : out    std_logic;
   18  --     o1 : out    std_logic;
   19  --     o2 : out    std_logic;
   20  --     o3 : out    std_logic;
   21  --     o4 : out    std_logic;
   22  --     o5 : out    std_logic;
   23  --     o6 : out    std_logic);
   24  -- 
   25  -- EASE/HDL end ----------------------------------------------------------------
   26  
   27  architecture a0 of To_digital is
   28  
   29  begin
   30     o0 <= To_X01(i0);
   31     o1 <= To_X01(i1);
   32     o2 <= To_X01(i2);
   33     o3 <= To_X01(i3);
   34     o4 <= To_X01(i4);
   35     o5 <= To_X01(i5);
   36     o6 <= To_X01(i6);
   37  end architecture a0 ; -- of To_digital
   38