Generated by EASE/HDL for peterj on Mon Jul 02 10:55:30 2007
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Documentation for architecture MROD_X_Out/Sharc/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Sharc'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     tredy     :  time := 5 ns;
   11  --     MS0_Wait  :  natural := 3;
   12  --     MS1_Wait  :  natural := 1;
   13  --     MS2_Wait  :  natural := 3;
   14  --     MS3_Wait  :  natural := 0;
   15  --     MS0_Hold  :  natural := 0;
   16  --     MS1_hold  :  natural := 0;
   17  --     MS2_Hold  :  natural := 1;
   18  --     MS3_Hold  :  natural := 0;
   19  --     MS0_Ack   :  boolean := True;
   20  --     MS1_Ack   :  boolean := True;
   21  --     MS2_Ack   :  boolean := False;
   22  --     MS3_Ack   :  boolean := True;
   23  --     Adr_Width :  positive := 32;
   24  --     Tcclk     :  time := 10000 ps);
   25  --   port(
   26  --     A_i       : in     std_logic_vector(31 downto 0);
   27  --     Ack       : in     std_logic;
   28  --     Adr       : inout  std_logic_vector(Adr_Width-1 downto 0);
   29  --     Cs_n      : in     std_logic;
   30  --     D_i       : in     std_logic_vector(31 downto 0);
   31  --     Data      : out    std_logic_vector(31 downto 0);
   32  --     HBG_n     : buffer std_logic;
   33  --     HBR_n     : in     std_logic;
   34  --     MS0_n     : out    std_logic;
   35  --     MS1_n     : out    std_logic;
   36  --     MS2_n     : out    std_logic;
   37  --     MS3_n     : out    std_logic;
   38  --     Rd_MS0    : in     std_logic;
   39  --     Rd_MS1    : in     std_logic;
   40  --     Rd_MS2    : in     std_logic;
   41  --     Rd_MS3    : in     std_logic;
   42  --     Rd_n      : inout  std_logic;
   43  --     Redy      : out    std_logic := '1';
   44  --     Rst_n     : in     std_logic;
   45  --     SBTS_n    : in     std_logic;
   46  --     Sharc_Clk : in     std_logic;
   47  --     Wr_MS0    : in     std_logic;
   48  --     Wr_MS1    : in     std_logic;
   49  --     Wr_MS2    : in     std_logic;
   50  --     Wr_MS3    : in     std_logic;
   51  --     Wr_n      : inout  std_logic);
   52  -- 
   53  -- EASE/HDL end ----------------------------------------------------------------
   54  
   55  architecture a0 of Sharc is
   56  --Tdhbgo:   HBG Delay after CLKIN
   57  --NOTE TBD!
   58    constant Tdhbgo: Time := 9 ns;
   59  
   60  --Tdaddo:   Address, MSx Delay After CLKIN
   61    constant Tdaddo: Time := 10 ns;
   62  
   63  --Tddato:   Data Delay After CLKIN
   64    constant Tddato: Time := 12500 ps;
   65  
   66  --Tdrwl:    RD/WR Low DelayAfter CLKIN
   67    constant Tdrwl: Time := Tcclk/4 + 9000 ps;
   68  
   69  --Thaddo:   Address, MSx Hold After CLKIN
   70    constant Thaddo: Time := 1500 ps;
   71  
   72  --Thdato:   Data Hold After CLKIN
   73    constant Thdato: Time := 1500 ps;
   74  
   75  --Tdrdo:    RD High Delay After CLKIN
   76  --Watch out! At 50 MHZ (Tcclk = 10 ns) Tdrdo can be 1500 ps to 11500 ps
   77  --worst = lower limit
   78    constant Tdrdo: Time := Tcclk/4 - 1000 ps;
   79  
   80  --Tdwdo:    WR High Delay After CLKIN
   81  --Watch out! At 50 MHZ (Tcclk = 10 ns) Tdwro can be 1500 ps to 11500 ps
   82  --worst = lower limit
   83    constant Tdwro: Time := Tcclk/4 - 1000 ps;
   84  
   85  --Tdrdyrdl: REDY Low Delay After RD Low
   86    constant Tdrdyrdl: Time := 10 ns;
   87  
   88  --Tsdatrdy: Data Valid Before REDY Disable from Low
   89    constant Tsdatrdy: Time := 2 ns;
   90  
   91  --Thdarw:   Data Disable After RD High
   92    constant Thdarwh: Time := 2 ns;
   93  
   94    Signal DataCyclePending: Std_logic := '0';
   95  begin
   96     
   97  HBRequest:
   98     Process (Sharc_Clk, Rst_n)
   99     Begin
  100        If Rst_n = '0' Then
  101           hbg_n <= '1';
  102        ElsIf Sharc_Clk = '1' And Sharc_Clk'Event Then
  103           hbg_n <=  hbr_n After tdhbgo;
  104        End If;
  105     End Process;
  106  
  107  REDY_Generation:
  108     process (wr_n, rd_n, cs_n, Rst_n)
  109     begin
  110        If Rst_n = '0' Then
  111           redy <= '0'; 
  112        ElsIf ((cs_n = '0' and wr_n = '0' and wr_n'event) or
  113               (cs_n = '0' and rd_n = '0' and rd_n'event)) then
  114           redy <= TRANSPORT '0' after Tdrdyrdl, '1' AFTER Tdrdyrdl + tredy;
  115        end if;
  116     end process;
  117  
  118  MS_Cycles:
  119     process (Sharc_Clk, hbg_n, cs_n, rd_n, Rst_n)
  120        Variable MS0_Busy: natural := 0;
  121        Variable MS1_Busy: natural := 0;
  122        Variable MS2_Busy: natural := 0;
  123        Variable MS3_Busy: natural := 0;
  124  
  125        Variable WaitCycle: integer := -1;
  126        Variable HoldCycle: integer := -1;
  127     Begin
  128        If Rst_n = '0' Then
  129           rd_n <= 'Z' after Tdrdo;
  130           wr_n <= 'Z' after Tdwro;
  131           MS0_n <= 'Z' after Thaddo;
  132           MS1_n <= 'Z' after Thaddo;
  133           MS2_n <= 'Z' after Thaddo;
  134           MS3_n <= 'Z' after Thaddo;
  135           adr <= (others => 'Z') after Thaddo;
  136           Data <= (others => 'Z') after Thdato;
  137        ElsIf hbg_n = '1' Then
  138           If Sharc_Clk'Event And Sharc_Clk= '1' Then
  139  
  140              --If No Ack and a cycle is in progress then count the wait cycles
  141              --and eventualy a hold cycle
  142              If (((MS0_Busy = 1) And (MS0_Ack = False)) Or 
  143                  ((MS1_Busy = 1) And (MS1_Ack = False)) Or 
  144                  ((MS2_Busy = 1) And (MS2_Ack = False)) Or
  145                  ((MS3_Busy = 1) And (MS3_Ack = False))) then
  146                 waitcycle := waitcycle + 1;
  147                 If ((MS0_Busy = 1) And (WaitCycle >= MS0_Wait)) Or
  148                    ((MS1_Busy = 1) And (WaitCycle >= MS1_Wait)) Or
  149                    ((MS2_Busy = 1) And (WaitCycle >= MS2_Wait)) Or
  150                    ((MS3_Busy = 1) And (WaitCycle >= MS3_Wait)) Then
  151                    HoldCycle := HoldCycle + 1;
  152                 End If;
  153              end if;
  154  
  155              --If wait cycles expired then end the read and write signals
  156              if (((MS0_Busy = 1) And (MS0_Ack = False) AND (waitcycle >= MS0_Wait)) Or
  157                  ((MS1_Busy = 1) And (MS1_Ack = False) AND (waitcycle >= MS1_Wait)) Or
  158                  ((MS2_Busy = 1) And (MS2_Ack = False) AND (waitcycle >= MS2_Wait)) Or
  159                  ((MS3_Busy = 1) And (MS3_Ack = False) AND (waitcycle >= MS3_Wait))) then
  160                 rd_n <= '1' after Tdrdo;
  161                 wr_n <= '1' after Tdwro;
  162              end if;
  163  
  164              --If hold cycles expired then end the whole cycle
  165              If (((MS0_Busy = 1) And
  166                  (((MS0_Ack = False) AND (WaitCycle >= MS0_Wait) And (HoldCycle >= MS0_Hold)) Or
  167                   ((MS0_Ack = True) AND ((Ack = '1') OR (Ack = 'H'))))) Or
  168                  ((MS1_Busy = 1) And
  169                   (((MS1_Ack = False) AND (WaitCycle >= MS1_Wait) And (HoldCycle >= MS1_Hold)) Or
  170                   ((MS1_Ack = True) AND ((Ack = '1') OR (Ack = 'H'))))) Or
  171                  ((MS2_Busy = 1) And
  172                   (((MS2_Ack = False) AND (WaitCycle >= MS2_Wait) And (HoldCycle >= MS2_Hold)) Or
  173                   ((MS2_Ack = True) AND ((Ack = '1') OR (Ack = 'H'))))) Or
  174                  ((MS3_Busy = 1) And
  175                   (((MS3_Ack = False) AND (WaitCycle >= MS3_Wait) And (HoldCycle >= MS3_Hold)) Or
  176                   ((MS3_Ack = True) AND ((Ack = '1') OR (Ack = 'H')))))) Then
  177                 MS0_Busy := 0;
  178                 MS1_Busy := 0;
  179                 MS2_Busy := 0;
  180                 MS3_Busy := 0;
  181                 rd_n <= Transport 'Z' after Tdrdo;
  182                 wr_n <= Transport 'Z' after Tdwro;
  183                 MS0_n <= Transport 'Z' after Thaddo;
  184                 MS1_n <= Transport 'Z' after Thaddo;
  185                 MS2_n <= Transport 'Z' after Thaddo;
  186                 MS3_n <= Transport 'Z' after Thaddo;
  187                 adr <= Transport (others => 'Z') after Thaddo;
  188             Data <= Transport (others => 'Z') after Thdato;
  189              End If;
  190  
  191              --Start of the cycles 
  192              If Rd_MS0 = '1' then
  193                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  194                 MS0_Busy := 1;
  195                 MS1_Busy := 0;
  196                 MS2_Busy := 0;
  197                 MS3_Busy := 0;
  198                 WaitCycle := -1;
  199                 HoldCycle := -1;
  200                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  201             Data <= Transport (others => 'Z') after Tddato;
  202                 rd_n <= Transport '0' after Tdrwl;
  203                 Wr_n <= Transport '1' after Tdrwl;
  204                 ms0_n <= Transport '0' after Tdaddo;
  205                 ms1_n <= Transport '1' after Tdaddo;
  206                 ms2_n <= Transport '1' after Tdaddo;
  207                 ms3_n <= Transport '1' after Tdaddo;
  208              ElsIf Wr_MS0 = '1' then
  209                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  210                 MS0_Busy := 1;
  211                 MS1_Busy := 0;
  212                 MS2_Busy := 0;
  213                 MS3_Busy := 0;
  214                 WaitCycle := -1;
  215                 HoldCycle := -1;
  216                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  217             Data <= Transport D_I after Tddato;
  218                 rd_n <= Transport '1' after Tdrwl;
  219                 Wr_n <= Transport '0' after Tdrwl;
  220                 ms0_n <= Transport '0' after Tdaddo;
  221                 ms1_n <= Transport '1' after Tdaddo;
  222                 ms2_n <= Transport '1' after Tdaddo;
  223                 ms3_n <= Transport '1' after Tdaddo;
  224              ElsIf Rd_MS1 = '1' then
  225                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  226                 MS0_Busy := 0;
  227                 MS1_Busy := 1;
  228                 MS2_Busy := 0;
  229                 MS3_Busy := 0;
  230                 WaitCycle := -1;
  231                 HoldCycle := -1;
  232                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  233             Data <= Transport (others => 'Z') after Tddato;
  234                 rd_n <= Transport '0' after Tdrwl;
  235                 Wr_n <= Transport '1' after Tdrwl;
  236                 ms0_n <= Transport '1' after Tdaddo;
  237                 ms1_n <= Transport '0' after Tdaddo;
  238                 ms2_n <= Transport '1' after Tdaddo;
  239                 ms3_n <= Transport '1' after Tdaddo;
  240              ElsIf Wr_MS1 = '1' then
  241                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  242                 MS0_Busy := 0;
  243                 MS1_Busy := 1;
  244                 MS2_Busy := 0;
  245                 MS3_Busy := 0;
  246                 WaitCycle := -1;
  247                 HoldCycle := -1;
  248                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  249             Data <= Transport D_I after Tddato;
  250                 rd_n <= Transport '1' after Tdrwl;
  251                 Wr_n <= Transport '0' after Tdrwl;
  252                 ms0_n <= Transport '1' after Tdaddo;
  253                 ms1_n <= Transport '0' after Tdaddo;
  254                 ms2_n <= Transport '1' after Tdaddo;
  255                 ms3_n <= Transport '1' after Tdaddo;
  256              ElsIf Rd_MS2 = '1' then
  257                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  258                 MS0_Busy := 0;
  259                 MS1_Busy := 0;
  260                 MS2_Busy := 1;
  261                 MS3_Busy := 0;
  262                 WaitCycle := -1;
  263                 HoldCycle := -1;
  264                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  265             Data <= Transport (others => 'Z') after Tddato;
  266                 rd_n <= Transport '0' after Tdrwl;
  267                 Wr_n <= Transport '1' after Tdrwl;
  268                 ms0_n <= Transport '1' after Tdaddo;
  269                 ms1_n <= Transport '1' after Tdaddo;
  270                 ms2_n <= Transport '0' after Tdaddo;
  271                 ms3_n <= Transport '1' after Tdaddo;
  272              ElsIf Wr_MS2 = '1' then
  273                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  274                 MS0_Busy := 0;
  275                 MS1_Busy := 0;
  276                 MS2_Busy := 1;
  277                 MS3_Busy := 0;
  278                 WaitCycle := -1;
  279                 HoldCycle := -1;
  280                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  281             Data <= Transport D_I after Tddato;
  282                 rd_n <= Transport '1' after Tdrwl;
  283                 Wr_n <= Transport '0' after Tdrwl;
  284                 ms0_n <= Transport '1' after Tdaddo;
  285                 ms1_n <= Transport '1' after Tdaddo;
  286                 ms2_n <= Transport '0' after Tdaddo;
  287                 ms3_n <= Transport '1' after Tdaddo;
  288              ElsIf Rd_MS3 = '1' then
  289                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  290                 MS0_Busy := 0;
  291                 MS1_Busy := 0;
  292                 MS2_Busy := 0;
  293                 MS3_Busy := 1;
  294                 WaitCycle := -1;
  295                 HoldCycle := -1;
  296                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  297             Data <= Transport (others => 'Z') after Tddato;
  298                 rd_n <= Transport '0' after Tdrwl;
  299                 Wr_n <= Transport '1' after Tdrwl;
  300                 ms0_n <= Transport '1' after Tdaddo;
  301                 ms1_n <= Transport '1' after Tdaddo;
  302                 ms2_n <= Transport '1' after Tdaddo;
  303                 ms3_n <= Transport '0' after Tdaddo;
  304              ElsIf Wr_MS3 = '1' then
  305                 ASSERT Not((MS0_Busy = 1) Or (MS1_Busy = 1) Or (MS2_Busy = 1) Or (MS3_Busy = 1)) Report LF & "Cycle not complete yet, starting a new one." severity NOTE;
  306                 MS0_Busy := 0;
  307                 MS1_Busy := 0;
  308                 MS2_Busy := 0;
  309                 MS3_Busy := 1;
  310                 WaitCycle := -1;
  311                 HoldCycle := -1;
  312                 adr(Adr_Width-1 downto 0) <= A_I(Adr_Width-1 downto 0) after Tdaddo;
  313             Data <= Transport D_I after Tddato;
  314                 rd_n <= Transport '1' after Tdrwl;
  315                 Wr_n <= Transport '0' after Tdrwl;
  316                 ms0_n <= Transport '1' after Tdaddo;
  317                 ms1_n <= Transport '1' after Tdaddo;
  318                 ms2_n <= Transport '1' after Tdaddo;
  319                 ms3_n <= Transport '0' after Tdaddo;
  320              End If;
  321           end if;
  322        Else
  323           -- If CS_n = '0' Then Asyncronous access
  324           -- Signal DataCyclePending holds off the Synchronous Data update during a rising
  325           -- edge Clock when an Asynchronous Rd cycle ended
  326           If CS_n = '0' Then
  327          If (rd_n = '0' and rd_n'event) Then
  328                 -- Data is valid Tsdatrdy before Redy goes high. Redy goes low Tdrdyrdl after
  329                 -- Rd_n and CS_n so data is valid Tdrdyrdl - Tsdatrdy + Tredy
  330                 Data <= D_I after (Tdrdyrdl - Tsdatrdy + Tredy);
  331                 DataCyclePending <= '1' after (Tdrdyrdl - Tsdatrdy + Tredy);
  332              ElsIf (rd_n = '1' and rd_n'event) Then
  333                 Data <= (others => 'Z') after Thdarwh;
  334                 DataCyclePending <= '0' after Thdarwh;
  335              end if;
  336           -- End Asynchronous access
  337           ElsIf (CS_n = '1' and CS_n'event) Then
  338              Data <= (others => 'Z') after Thdarwh;
  339              DataCyclePending <= '0' after Thdarwh;
  340           -- Syncronous access
  341           Else
  342              ms0_n <= 'Z' after Thaddo;
  343              ms1_n <= 'Z' after Thaddo;
  344              ms2_n <= 'Z' after Thaddo;
  345              ms3_n <= 'Z' after Thaddo;
  346              adr <= (others => 'Z') after Thaddo;
  347              rd_n <= 'Z' after Tdrdo;
  348              wr_n <= 'Z' after Tdwro;
  349              If DataCyclePending = '0' Then
  350                 Data <= (others => 'Z') after Thdato;
  351              End If;
  352           End If;
  353        end if;
  354     end process;
  355  end architecture a0 ; -- of Sharc
  356