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MROD_X_Out

PulsGen

Documentation for architecture MROD_X_Out/PulsGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'PulsGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Number :  natural := 15);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     Pulse : out    std_logic;
   14  --     Rst_n : in     std_logic;
   15  --     Trig  : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of PulsGen is
   20  
   21  BEGIN
   22     Process (Clk, Rst_n)
   23        Variable PulseCnt: Integer Range 0 To Number;
   24     Begin
   25        If Rst_n = '0' Then
   26           Pulse <= '0';
   27           PulseCnt := 0;
   28        ElsIf Rising_Edge(Clk) Then
   29           If PulseCnt = number Then
   30              PulseCnt := 0;
   31              Pulse <= '0';
   32           ElsIf Trig = '1' And PulseCnt = 0 Then
   33              PulseCnt := PulseCnt + 1;
   34              Pulse <= '1';
   35           ElsIf PulseCnt /= 0 Then
   36              PulseCnt := PulseCnt + 1;
   37              Pulse <= '1';
   38           End If;
   39        End If;
   40     End Process;
   41  end architecture a0 ; -- of PulsGen
   42