Back

Index

MROD_X_Out

Latch1

Documentation for architecture MROD_X_Out/Latch1/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Latch1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     En    : in     std_logic;
   12  --     I     : in     std_logic;
   13  --     O     : out    std_logic;
   14  --     Rst_n : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Latch1 is
   19  
   20  begin
   21     Process (Clk, Rst_n)
   22     Begin
   23        If Rst_n = '0' Then
   24           O <= '0';
   25        ElsIf Rising_Edge(Clk) Then
   26           If En = '1' Then
   27              O <= I;
   28           End If;
   29        End If;
   30     End Process;
   31  end architecture a0 ; -- of Latch1
   32