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MROD_X_Out

DataBufferControl

Documentation for architecture MROD_X_Out/DataBufferControl/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DataBufferControl'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     AD_PHASE   : in     std_logic;
   11  --     DENIN0_n   : out    std_logic;
   12  --     DENIN1_n   : out    std_logic;
   13  --     DENO0_n    : out    std_logic;
   14  --     DENO1_n    : out    std_logic;
   15  --     DENO_n     : out    std_logic;
   16  --     DSB        : in     std_logic;
   17  --     LocBG_n    : in     std_logic;
   18  --     R_W_n      : in     std_logic;
   19  --     SWDEN_n    : out    std_logic;
   20  --     SWDENin_n  : in     std_logic;
   21  --     SlaveHit_n : in     std_logic);
   22  -- 
   23  -- EASE/HDL end ----------------------------------------------------------------
   24  
   25  architecture a0 of DataBufferControl is
   26  
   27  begin
   28     Process(AD_PHASE, SlaveHit_n, DSB, SWDENin_n, R_W_n, LocBG_n)
   29     Begin
   30        If LocBG_n = '0' Then
   31           If AD_PHASE = '1' Then
   32              DENO_n <= '1';   --Disable drivers to VME bus
   33              DENO0_n <= '1';  --Disable drivers [15..0] of databus out of FPGA
   34              DENO1_n <= '1';  --Disable drivers [31..16] of databus out of FPGA
   35              DENIN0_n <= '0';  --Enable VME databus to local bus so the upper addres
   36              DENIN1_n <= '0'; --bits can be captured from the datalines.
   37              SWDEN_n <= '1';
   38           ElsIf SlaveHit_n = '0' And DSB = '1' Then
   39              If R_W_n = '0' Then   --Write
   40                 DENO_n <= '1';     --Disable drivers to VME bus
   41                 DENO0_n <= '1';    --Disable drivers [31..0] of databus out of FPGA
   42                 DENO1_n <= '1';
   43                 If SWDENin_n = '1' Then
   44                    --Write No Swap:
   45                    DENIN0_n <= '0'; --Enable all VME to local data lines
   46                    DENIN1_n <= '0';
   47                    SWDEN_n <= '1';
   48                 Else
   49                    --Write And Swap VME D[15..0] to Local D[31..15]:
   50                    DENIN0_n <= '0'; --Only enable the lower VME data lines
   51                    DENIN1_n <= '1';
   52                    SWDEN_n <= '0';  --Only Swap during DSB true
   53                 End If;
   54              Else                   --Read
   55                 DENIN0_n <= '1';    --Disable drivers to Local bus
   56                 DENIN1_n <= '1';
   57                 DENO_n <= '0';      -- Enable drivers to VME bus
   58                 If SWDENin_n = '1' Then
   59                    --Read No Swap:
   60                    DENO0_n <= '0';
   61                    DENO1_n <= '0';
   62                    SWDEN_n <= '1';
   63                 Else
   64                    --Read And Swap Local D[31..16] to VME D[15..0]:
   65                    DENO0_n <= '1';
   66                    DENO1_n <= '0';  --Only enable the upper Local data lines
   67                    SWDEN_n <= '0';  --Only Swap during DSB true
   68                 End If;
   69              End If;
   70           Else
   71              DENO_n <= '1';
   72              DENO0_n <= '1';
   73              DENO1_n <= '1';
   74              DENIN0_n <= '1';
   75              DENIN1_n <= '1';
   76              SWDEN_n <= '1';
   77           End If;
   78        Else
   79           DENO_n <= '1';
   80           DENO0_n <= '1';
   81           DENO1_n <= '1';
   82           DENIN0_n <= '1';
   83           DENIN1_n <= '1';
   84           SWDEN_n <= '1';
   85        End If;
   86     End Process;
   87  end architecture a0 ; -- of DataBufferControl
   88