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MROD_X_Out

AndG4

Documentation for architecture MROD_X_Out/AndG4/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AndG4'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A : in     std_logic;
   11  --     B : in     std_logic;
   12  --     C : in     std_logic;
   13  --     D : in     std_logic;
   14  --     O : out    std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of AndG4 is
   19  
   20  BEGIN
   21     O <= A And B And C And D;
   22  end architecture a0 ; -- of AndG4
   23