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MROD_X_Out

WEN_Logic

Documentation for architecture MROD_X_Out/WEN_Logic/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'WEN_Logic.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'WEN_Logic' :
    5  -- 
    6  --   port(
    7  --     EnPipe_n     : out    std_logic;
    8  --     LFF          : out    std_logic;
    9  --     LFF_n        : in     std_logic;
   10  --     MS3_n        : in     std_logic;
   11  --     Sync_LDOWN_n : in     std_logic;
   12  --     UWEN_n       : out    std_logic;
   13  --     Wr_n         : in     std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of WEN_Logic is
   18  
   19  BEGIN
   20  
   21     LFF <= Not LFF_n;
   22  
   23     UWEN_Proc:
   24     Process (Wr_n, MS3_n, Sync_LDOWN_n)
   25     Begin
   26        If Wr_n = '0' And MS3_n = '0' And Sync_LDOWN_n = '1' Then
   27           UWEN_n <= '0';
   28        Else
   29           UWEN_n <= '1';
   30        End If;
   31     End Process;
   32  
   33  --Pipeline is enabled when written to MS3_n 
   34  --provided the S_LINK is up and not full
   35     EnPipe_Proc:
   36     Process (Wr_n, MS3_n, LFF_n, Sync_LDOWN_n)
   37     Begin
   38        If Wr_n = '0' And MS3_n = '0' And Sync_LDOWN_n = '1' And LFF_n = '1' Then
   39           EnPipe_n <= '0';
   40        Else
   41           EnPipe_n <= '1';
   42        End If;
   43     End Process;
   44  end architecture a0 ; -- of WEN_Logic
   45