Generated by EASE/HDL for peterj on Mon Jul 02 10:55:31 2007
Back Index MROD_X_Out tma

Documentation for architecture MROD_X_Out/tma/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'tma'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Slot1Master :  boolean := True;
   11  --     CommandFile :  String := "vme.cmd");
   12  --   port(
   13  --     A          : inout  std_logic_vector(31 downto 1);
   14  --     ACFAIL_n   : inout  std_logic;
   15  --     AM         : inout  std_logic_vector(5 downto 0);
   16  --     AS_n       : inout  std_logic;
   17  --     BBSY_n     : inout  std_logic;
   18  --     BCLR_n     : inout  std_logic;
   19  --     BERR_n     : inout  std_logic;
   20  --     BG3IN_n    : in     std_logic;
   21  --     BG3OUT_n   : out    std_logic;
   22  --     BR3_n      : inout  std_logic;
   23  --     D          : inout  std_logic_vector(31 downto 0);
   24  --     DS_n       : inout  std_logic_vector(1 downto 0);
   25  --     DTACK_n    : inout  std_logic;
   26  --     DoVME      : in     std_logic;
   27  --     FastVME    : in     std_logic;
   28  --     IACKIN_n   : in     std_logic;
   29  --     IACKOUT_n  : out    std_logic;
   30  --     IACK_n     : inout  std_logic;
   31  --     IRQ_n      : inout  std_logic_vector(7 downto 1);
   32  --     LWORD_n    : inout  std_logic;
   33  --     SYSFAIL_n  : inout  std_logic;
   34  --     SYSRESET_n : inout  std_logic;
   35  --     WRITE_n    : inout  std_logic);
   36  -- 
   37  -- EASE/HDL end ----------------------------------------------------------------
   38  
   39  architecture a0 of tma is
   40     -- moeten verschillende typedefs worden, zodat beter type-checking mogelijk is.
   41    type VmeCycle is (RD, WR, RMW, Long, Word, Byte, BlockT,Fast,  
   42              Typ, Slow,NoBlock,IackC);
   43    subtype stdbyte is std_logic_vector(7 downto 0);
   44    type bytearr is array (0 to 15) of stdbyte;
   45    signal BG3IN_n_local : std_logic;
   46    signal xbytebuf : bytearr;
   47  --  file cmdfile: TEXT is IN cmdfile;  -- 1987 standard
   48    file cmdfile: TEXT open READ_MODE is commandfile;  -- 1993 standard
   49    
   50    procedure vme_cycle(
   51                 VAM  : In  std_logic_vector(5 downto 0);
   52             VA   : In  std_logic_vector(31 downto 0);
   53             VD   : InOut  std_logic_vector(31 downto 0);
   54             CSize    : In     VmeCycle;
   55             Ctype    : In     VmeCycle;
   56             Cycles   : In     Natural;
   57             Speed    : In     VmeCycle;
   58             CBlock   : In     VmeCycle;
   59      signal Dbuf : InOut  ByteArr;
   60      signal AS_n : InOut  std_logic;
   61      signal AM   : Out  std_logic_vector(5 downto 0);
   62      signal A    : Out  std_logic_vector(31 downto 1);
   63      signal D    : InOut  std_logic_vector(31 downto 0);
   64      signal DS_n : InOut  std_logic_vector(1 downto 0);
   65      signal DTACK_n  : In     std_logic;
   66      signal BERR_n   : In     std_logic;
   67      signal WRITE_n  : InOut  std_logic;
   68      signal LWORD_n  : Out    std_logic;
   69      signal BR3_n    : Out    std_logic;
   70      signal BG3IN_n  : In     std_logic;
   71      signal IACK_n   : Out    std_logic;
   72      signal BBSY_n   : Out    std_logic
   73    ) is
   74  -- Aug. 20, 2003 PeterJ
   75  -- Changed to be compatible with package NUMERIC_STD
   76  --  variable LVA    : std_logic_vector(31 downto 0) := VA;
   77    variable LVA  : Unsigned(31 downto 0) := Unsigned(VA);
   78    variable DSB  : std_logic_vector(1 downto 0);
   79    variable bi, LCycles : Natural;
   80    variable bytebuf : bytearr;
   81    begin
   82      BR3_n <= '0';
   83      wait until BG3IN_n = '0' or BG3IN_n_local = '0';  -- last term is used when
   84                                -- tmod is slot1 master
   85      BBSY_n <= '0';
   86      BR3_n <= 'H' after 35 ns;
   87      if (Csize = Long) or (Csize = Word) then
   88      DSB := "00";
   89      elsif (VA(0) = '0') then
   90      DSB := "01";
   91      else
   92      DSB := "10";
   93      end if;
   94      if CType = RMW then
   95      LCycles := 2;
   96      else
   97      LCycles := Cycles;
   98      end if;
   99      for i in 1 to LCycles loop
  100        if ((CBlock /= BlockT) and (CType /= RMW)) or (i = 1) then
  101          if AS_n = '0' then
  102            wait until AS_n /= '0';
  103        wait for 45 ns;
  104          end if;
  105        end if;
  106  -- Aug. 20, 2003 PeterJ
  107  -- Changed to be compatible with package NUMERIC_STD
  108  --      A <= LVa(31 downto 1);
  109        A <= Std_Logic_Vector(LVa(31 downto 1));
  110        AM <= VAm; 
  111        AS_n <= '0';
  112        if (CType = WR) or ((CType = RMW) and (i = 2)) then 
  113          WRITE_n <= '0'; 
  114        else 
  115          WRITE_n <= '1';
  116        end if;
  117        if (Csize = Long) then
  118          LWORD_n <= '0';
  119        end if;
  120        if CType = IACKC then
  121          IACK_n <= '0';
  122        end if;
  123        Case Speed is 
  124        when Fast => wait for 10 ns;
  125        when Typ =>  wait for 30 ns;
  126        when Others => wait for 60 ns;
  127        end case;
  128        if (DTACK_n and BERR_n) = '0' then
  129          wait until (DTACK_n and BERR_n) /= '0';
  130        end if;
  131  --      AS_n <= '0';
  132        if WRITE_n = '0' then
  133          if (Csize = Long) then
  134  --    bi := (i-1)*4;
  135  --        D <= dbuf(bi) & dbuf(bi+1) & dbuf(bi+2) & dbuf(bi+3);
  136        D <= vd;  
  137          else
  138  --    bi := (i-1)*2;
  139  --    if DSB(1) = '0' then D(15 downto 8) <= dbuf(bi); end if;
  140  --    if DSB(0) = '0' then D(7 downto 0) <= dbuf(bi + 1); end if;
  141        if DSB(1) = '0' then D(15 downto 8) <= vd(15 downto 8) ; end if;
  142        if DSB(0) = '0' then D(7 downto 0) <= vd(7 downto 0); end if;     
  143          end if;
  144        end if;
  145        DS_n <= DSB;
  146  
  147        wait until (DTACK_n and BERR_n) = '0';
  148        if i = LCycles then
  149        -- wait until (DTACK_n and BERR_n) /= '0'; -- may BBSY_n be released
  150        -- directy after dtack_n low?
  151        BBSY_n <= 'H';
  152        end if;
  153        if WRITE_n /= '0' then
  154          if (Csize = Long) then
  155  --    bi := (i-1)*4;
  156  --          bytebuf(bi) := D(31 downto 24);
  157  --          bytebuf(bi+1) := D(23 downto 16);
  158  --          bytebuf(bi+2) := D(15 downto 8);
  159  --          bytebuf(bi+3) := D(7 downto 0);
  160          else
  161  --    bi := (i-1)*2;
  162  --    if DSB(1) = '0' then bytebuf(bi) := D(15 downto 8); end if;
  163  --    if DSB(0) = '0' then bytebuf(bi+1) := D(7 downto 0); end if;
  164          end if;
  165  --        Dbuf <= Bytebuf;
  166        end if;
  167        Case Speed is 
  168        when Fast => wait for 0 ns;
  169          if (CBlock /= BlockT) and (CType /= RMW) then
  170        LVA := LVA + 4;
  171      end if;
  172        when Typ =>  wait for 20 ns;
  173        when Others => wait for 40 ns;
  174        end case;
  175        DS_n <= "11";
  176        if (CBlock = BlockT) and (CSize = Byte) then
  177      DSB := not DSB;
  178        end if;
  179        if ((CBlock /= BlockT) and (CType /= RMW)) or (i = LCycles) then
  180          AS_n <= 'H';
  181          WRITE_n <= 'H';
  182          LWORD_n <= 'H';
  183          AM <= "HHHHHH";
  184          A <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  185          D <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  186          DS_n <= "HH";
  187          IACK_n <= 'H';
  188        end if;
  189      end loop;
  190      BBSY_n <= 'H';
  191    end;
  192  
  193    procedure to_upper(variable str: inout string) is
  194        variable i  : natural;
  195    begin
  196        for i in str'range loop
  197        str(i) := to_upper(str(i));
  198        end loop;  -- i
  199    end;
  200    
  201  begin
  202    AS_n <= 'H';
  203    AM <= "HHHHHH";
  204    A <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  205    D <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  206    DS_n <= "HH";
  207    IRQ_n <= "HHHHHHH";
  208    DTACK_n <= 'H';
  209    BERR_n <= 'H';
  210    BBSY_n <= 'H';
  211    BR3_n <= 'H';
  212    WRITE_n <= 'H';
  213    LWORD_n <= 'H';
  214    BCLR_n <= 'H';
  215    IACK_n <= 'H';
  216    SYSRESET_n <= 'H';
  217    SYSFAIL_n <= 'H';
  218    ACFAIL_n <= 'H';
  219    IACKOUT_n <= IACKIN_n;
  220  
  221    bus_arbiter : process (BR3_n,BBSY_n)
  222      begin  -- very primitive bus arbiter
  223          if Slot1Master = TRUE then
  224          if BR3_n'event and BR3_n = '0' then
  225              if BBSY_n = 'H' or BBSY_n = '1' then
  226              BG3IN_n_local <= '0' after 10 ns;
  227              end if;
  228          elsif BBSY_n'event and BBSY_n = '0' then
  229              BG3IN_n_local <= 'H' after 10 ns;
  230          end if;
  231          end if;
  232      end process;
  233  
  234    BG3OUT_n <= BG3IN_n_local;        -- not ok BG3OUT_n should not be
  235                      -- asserted when tmod requests the bus
  236      
  237    accrep : process              -- produces report string for the 
  238                      -- transcript window
  239    variable rd, err : string(1 to 6);
  240    variable sz : string(1 to 6);
  241  -- Aug. 20, 2003 PeterJ
  242  -- Changed to be compatible with package NUMERIC_STD
  243  --  variable la : std_logic_vector(31 downto 1);
  244  --  variable ld : std_logic_vector(31 downto 0);
  245    variable la : Unsigned(31 downto 1);
  246    variable ld : Unsigned(31 downto 0);
  247    begin
  248  --    wait for 393000 ns;
  249    loop
  250      wait until (DS_n(0) = '0') or (DS_n(1) = '0');
  251      wait for 30 ns;
  252  -- Aug. 20, 2003 PeterJ
  253  -- Changed to be compatible with package NUMERIC_STD
  254  --    la := A;
  255      la := Unsigned(A);
  256      if WRITE_n = '0' then
  257        rd := " WRITE";
  258      else
  259        rd := " READ ";
  260      end if;
  261      if LWORD_n = '0' then 
  262        sz := " LONG ";
  263      elsif DS_n = "00" then
  264        sz := " WORD ";
  265        if LA(1) = '0' then sz(6) := '0'; else sz(6) := '1'; end if;
  266      else
  267        sz := " BYTE ";
  268        if la(1) = '0' then
  269      if DS_n(1) = '0' then sz(6) := '0'; else sz(6) := '1'; end if;
  270        else
  271      if DS_n(1) = '0' then sz(6) := '2'; else sz(6) := '3'; end if;
  272        end if;
  273      end if;
  274      wait until (BERR_n = '0') or (DTACK_n = '0');
  275      if BERR_n = '0' then 
  276        err := " BERR "; 
  277      else
  278        case AM is
  279        when "111101" => err := " STSDA";
  280        when "111110" => err := " STSPA";
  281        when "111111" => err := " STSBL";
  282        when "110101" => err := " STNDA";
  283        when "110110" => err := " STNPA";
  284        when "110111" => err := " STNBL";
  285        when "001101" => err := " EXSDA";
  286        when "001110" => err := " EXSPA";
  287        when "001111" => err := " EXSBL";
  288        when "000101" => err := " EXNDA";
  289        when "000110" => err := " EXNPA";
  290        when "000111" => err := " EXNBL";
  291        when "101101" => err := " SHSA ";
  292        when "101001" => err := " SHNA ";
  293        when others =>   err := " RESRV";
  294        err := "      ";
  295        end case;
  296      end if;
  297      if BERR_n /= '0' then
  298  -- Aug. 20, 2003 PeterJ
  299  -- Changed to be compatible with package NUMERIC_STD
  300  --      LD := D(31 downto 0);
  301        LD := Unsigned(D(31 downto 0));
  302      else
  303        LD := "00000000000000000000000000000000";
  304      end if;
  305  -- Aug. 20, 2003 PeterJ
  306  -- Changed to be compatible with package NUMERIC_STD
  307  -- and package STD_DEVELOPERSKIT.std_iopak
  308  -- 'Print' changed into 'write(output,' in order to get rid
  309  -- of MMS.stdioimp.all
  310  --    print(tostring(now) & " VME  A: " &
  311  --    tostring(conv_integer(LA(31 downto 16)),"%04x") & 
  312  --    tostring(conv_integer(LA(15 downto 1) & '0'),"%04x") & 
  313  --    "  D: " &
  314  --    tostring(conv_integer(LD(31 downto 16)),"%04x") &
  315  --    tostring(conv_integer(LD(15 downto 0)),"%04x") &
  316  --    rd & sz & err
  317  --    );
  318        write(output,(to_string(now) & " VME  A: " &
  319        to_string(to_bitvector(Std_Logic_Vector(LA(31 downto 16))),"%x") & 
  320        to_string(to_bitvector(Std_Logic_Vector(LA(15 downto 1) & '0')),"%x") & 
  321        "  D: " &
  322        to_string(to_bitvector(Std_Logic_Vector(LD(31 downto 16))),"%x") &
  323        to_string(to_bitvector(Std_Logic_Vector(LD(15 downto 0))),"%x") &
  324  
  325  --    To_HexString(Std_Logic_Vector(LA(31 downto 1) & '0')) & 
  326  --    "  D: " &
  327  --    To_HexString(Std_Logic_Vector(LD(31 downto 0))) &
  328  
  329        rd & sz & err & cr)
  330      );
  331      wait until to_x01(DS_n) = "11";
  332    end loop;
  333    end process;
  334  
  335    master1 : process
  336        variable Vam : std_logic_vector(5 downto 0) := "111101"; -- 0x3d
  337        variable Va : std_logic_vector(31 downto 0) := "10000000000000000000000000000000";
  338        variable Vd : std_logic_vector(31 downto 0) := "11000000000000000000000000000000";
  339        variable ctype, csize, cmode : vmecycle ;
  340        variable delay : time;
  341        variable num_cycles : natural := 1;
  342        variable lin : LINE;
  343        variable str : string(1 to 256) := (others => ' ');
  344        variable time_str, am_str, ctype_str, csize_str, numc_str : string(1 to 16) := (others => ' ');
  345        variable addr_str, data_str : string(1 to 16) := (others => ' ');
  346    begin
  347      AS_n <= 'H';
  348      AM <= "HHHHHH";
  349      A <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  350      D <= "HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH";
  351      DS_n <= "HH";
  352      DTACK_n <= 'H';
  353      BERR_n <= 'H';
  354      BR3_n <= 'H';
  355      WRITE_n <= 'H';
  356      LWORD_n <= 'H';
  357      IACK_n <= 'H';
  358      BBSY_n <= 'H';
  359  --    wait until StartArr(0) = '1';
  360      wait for 100 ns;
  361  
  362      readfile : while ENDFILE(cmdfile) = FALSE loop
  363  
  364      fgetline(str,cmdfile,lin);      -- read one line from file
  365          time_str := (others => ' ');
  366          am_str := (others => ' ');
  367          ctype_str := (others => ' ');
  368          csize_str := (others => ' ');
  369          addr_str := (others => ' ');
  370          data_str := (others => ' ');
  371      fscan(str,"%t %x %s %s %d %x %x",time_str,am_str, ctype_str, csize_str, numc_str, addr_str, data_str);  -- assign to (string) variables
  372  
  373      delay := From_String(time_str);
  374      vam := To_StdLogicVector(From_HexString(am_str)(5 downto 0));
  375          To_Upper(ctype_str);
  376      if StrCmp(ctype_str, "RD") = 0  then
  377          ctype := RD;
  378      elsif StrCmp(ctype_str, "WR") = 0 then
  379          ctype := WR;
  380      elsif StrCmp(ctype_str, "RMW") = 0 then
  381          ctype := RMW;
  382      elsif StrCmp(ctype_str, "IACKC") = 0 then
  383          ctype := IACKC;
  384      else
  385          assert false
  386          report "vme cycle not executed." & LF &
  387                 "  unknown cycle type: " & ctype_str
  388          severity warning;
  389          next;
  390      end if;
  391          To_Upper(csize_str);
  392      if StrCmp(csize_str, "LONG") = 0 then
  393          csize := Long;
  394      elsif StrCmp(csize_str, "WORD") = 0 then
  395          csize := Word;
  396      elsif StrCmp(csize_str, "BYTE") = 0 then
  397          csize := Byte;
  398      else
  399          assert false
  400          report "vme cycle not executed." & LF &
  401                 "  unknown data size: " & csize_str
  402          severity warning;
  403          next;
  404      end if;
  405  
  406      num_cycles := From_String(numc_str);
  407          if (num_cycles > 1) then
  408              cmode := BlockT;
  409          else 
  410              cmode := NoBlock;
  411          end if;
  412  
  413          
  414      va := (others => '0');
  415      va(From_HexString(addr_str)'length-1 downto 0) := To_StdLogicVector(From_HexString(addr_str));
  416      vd := (others => '0');
  417      vd(From_HexString(data_str)'length-1 downto 0) := To_StdLogicVector(From_HexString(data_str));
  418          wait for delay;
  419  
  420          If DoVME = '1' Then
  421             If FastVME = '1' Then
  422                vme_cycle(vam, va, vd, csize, ctype, num_cycles, fast, cmode, Xbytebuf, AS_n, AM, A, D, DS_n, DTACK_n, BERR_n, WRITE_n, LWORD_n, BR3_n, BG3IN_n, IACK_n, BBSY_n);
  423             Else
  424                vme_cycle(vam, va, vd, csize, ctype, num_cycles, slow, cmode, Xbytebuf, AS_n, AM, A, D, DS_n, DTACK_n, BERR_n, WRITE_n, LWORD_n, BR3_n, BG3IN_n, IACK_n, BBSY_n);
  425             End IF;
  426          End If;
  427      end loop readfile;
  428  
  429      
  430  --    vme_cycle(vam, va, vd, Byte, RMW, 2, fast, NoBlock, Xbytebuf, AS_n, AM, A, D, DS_n, DTACK_n, BERR_n, WRITE_n, LWORD_n, BR3_n, BG3IN_n, IACK_n, BBSY_n);  
  431      wait; -- no more action
  432    end process;
  433  end architecture a0 ; -- of tma
  434