Generated by EASE/HDL for peterj on Mon Jul 02 10:55:29 2007
Back Index MROD_X_Out Pullup1

Documentation for architecture MROD_X_Out/Pullup1/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Pullup1'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     O : out    std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of Pullup1 is
   15  
   16  begin
   17     O <= 'H';
   18  end architecture a0 ; -- of Pullup1
   19